Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4611720 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1109 |
| auto[1] |
2421026 |
1 |
|
|
T1 |
875 |
|
T11 |
3132 |
|
T18 |
94 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730984 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1959 |
| auto[1] |
301762 |
1 |
|
|
T1 |
25 |
|
T11 |
225 |
|
T18 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4624081 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1092 |
| auto[1] |
2408665 |
1 |
|
|
T1 |
892 |
|
T11 |
2317 |
|
T18 |
125 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1059225 |
1 |
|
|
T1 |
521 |
|
T11 |
1026 |
|
T18 |
79 |
| auto[1] |
auto[0] |
auto[1] |
151307 |
1 |
|
|
T1 |
15 |
|
T11 |
108 |
|
T18 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1047678 |
1 |
|
|
T1 |
346 |
|
T11 |
1066 |
|
T18 |
38 |
| auto[1] |
auto[1] |
auto[1] |
150455 |
1 |
|
|
T1 |
10 |
|
T11 |
117 |
|
T26 |
3052 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |