Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4630311 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1013 |
| auto[1] |
2402435 |
1 |
|
|
T1 |
971 |
|
T11 |
2183 |
|
T18 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727710 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
1941 |
| auto[1] |
305036 |
1 |
|
|
T1 |
43 |
|
T11 |
195 |
|
T18 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4610993 |
1 |
|
|
T24 |
205 |
|
T25 |
600 |
|
T1 |
885 |
| auto[1] |
2421753 |
1 |
|
|
T1 |
1099 |
|
T11 |
2148 |
|
T18 |
74 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1073012 |
1 |
|
|
T1 |
523 |
|
T11 |
969 |
|
T18 |
34 |
| auto[1] |
auto[0] |
auto[1] |
155485 |
1 |
|
|
T1 |
22 |
|
T11 |
87 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1043705 |
1 |
|
|
T1 |
533 |
|
T11 |
984 |
|
T18 |
34 |
| auto[1] |
auto[1] |
auto[1] |
149551 |
1 |
|
|
T1 |
21 |
|
T11 |
108 |
|
T18 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |