Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 945
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T764 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3360340027 Aug 19 04:38:40 PM PDT 24 Aug 19 04:38:41 PM PDT 24 14244335 ps
T765 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3941975520 Aug 19 04:38:14 PM PDT 24 Aug 19 04:38:16 PM PDT 24 72776677 ps
T766 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.534118865 Aug 19 04:38:21 PM PDT 24 Aug 19 04:38:24 PM PDT 24 94499611 ps
T75 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1969732166 Aug 19 04:38:36 PM PDT 24 Aug 19 04:38:36 PM PDT 24 11322033 ps
T81 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1301845625 Aug 19 04:38:28 PM PDT 24 Aug 19 04:38:29 PM PDT 24 34378158 ps
T767 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.98738147 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:28 PM PDT 24 27160055 ps
T768 /workspace/coverage/cover_reg_top/41.gpio_intr_test.575462089 Aug 19 04:38:41 PM PDT 24 Aug 19 04:38:42 PM PDT 24 61534274 ps
T769 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1102016782 Aug 19 04:38:16 PM PDT 24 Aug 19 04:38:18 PM PDT 24 228329383 ps
T770 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3565294642 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:29 PM PDT 24 14122959 ps
T82 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2398740124 Aug 19 04:38:16 PM PDT 24 Aug 19 04:38:16 PM PDT 24 76168275 ps
T44 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.377826225 Aug 19 04:38:13 PM PDT 24 Aug 19 04:38:14 PM PDT 24 688708575 ps
T43 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3729688911 Aug 19 04:38:15 PM PDT 24 Aug 19 04:38:16 PM PDT 24 121960728 ps
T771 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2249429456 Aug 19 04:38:14 PM PDT 24 Aug 19 04:38:15 PM PDT 24 24781831 ps
T772 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3608078760 Aug 19 04:38:23 PM PDT 24 Aug 19 04:38:23 PM PDT 24 62219149 ps
T89 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2650146363 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:28 PM PDT 24 296023208 ps
T773 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.530139705 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:30 PM PDT 24 14254786 ps
T774 /workspace/coverage/cover_reg_top/49.gpio_intr_test.1993864008 Aug 19 04:38:38 PM PDT 24 Aug 19 04:38:39 PM PDT 24 44431785 ps
T775 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1892131851 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:29 PM PDT 24 439973189 ps
T83 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2610583288 Aug 19 04:38:14 PM PDT 24 Aug 19 04:38:15 PM PDT 24 25333037 ps
T776 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2780304912 Aug 19 04:38:31 PM PDT 24 Aug 19 04:38:31 PM PDT 24 17513472 ps
T84 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1127668087 Aug 19 04:38:17 PM PDT 24 Aug 19 04:38:18 PM PDT 24 32770099 ps
T777 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1322979079 Aug 19 04:38:19 PM PDT 24 Aug 19 04:38:20 PM PDT 24 12200804 ps
T778 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1313657243 Aug 19 04:38:41 PM PDT 24 Aug 19 04:38:41 PM PDT 24 62974735 ps
T779 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2096361230 Aug 19 04:38:13 PM PDT 24 Aug 19 04:38:14 PM PDT 24 27673820 ps
T780 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2135189281 Aug 19 04:38:41 PM PDT 24 Aug 19 04:38:41 PM PDT 24 22677765 ps
T781 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3416067208 Aug 19 04:38:28 PM PDT 24 Aug 19 04:38:29 PM PDT 24 27624991 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2139431689 Aug 19 04:38:08 PM PDT 24 Aug 19 04:38:09 PM PDT 24 321193083 ps
T783 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.577695102 Aug 19 04:38:13 PM PDT 24 Aug 19 04:38:14 PM PDT 24 93425851 ps
T784 /workspace/coverage/cover_reg_top/26.gpio_intr_test.4277244501 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:30 PM PDT 24 40635381 ps
T785 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2600352456 Aug 19 04:38:12 PM PDT 24 Aug 19 04:38:13 PM PDT 24 53802425 ps
T786 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1781704630 Aug 19 04:38:18 PM PDT 24 Aug 19 04:38:19 PM PDT 24 17301518 ps
T76 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1111828894 Aug 19 04:38:07 PM PDT 24 Aug 19 04:38:08 PM PDT 24 39912175 ps
T77 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2684220799 Aug 19 04:38:13 PM PDT 24 Aug 19 04:38:14 PM PDT 24 89968389 ps
T787 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2849934000 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:30 PM PDT 24 19575572 ps
T788 /workspace/coverage/cover_reg_top/46.gpio_intr_test.775135360 Aug 19 04:38:40 PM PDT 24 Aug 19 04:38:40 PM PDT 24 69899598 ps
T789 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2763432461 Aug 19 04:38:36 PM PDT 24 Aug 19 04:38:36 PM PDT 24 13295608 ps
T790 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2027426329 Aug 19 04:38:12 PM PDT 24 Aug 19 04:38:13 PM PDT 24 80268758 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1622229547 Aug 19 04:38:15 PM PDT 24 Aug 19 04:38:18 PM PDT 24 330349056 ps
T792 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3252487534 Aug 19 04:38:38 PM PDT 24 Aug 19 04:38:39 PM PDT 24 22787350 ps
T793 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3203071242 Aug 19 04:38:36 PM PDT 24 Aug 19 04:38:36 PM PDT 24 26617820 ps
T794 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2827970586 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:31 PM PDT 24 75574482 ps
T45 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.716788053 Aug 19 04:38:28 PM PDT 24 Aug 19 04:38:30 PM PDT 24 1348494008 ps
T795 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3993936881 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:28 PM PDT 24 43172068 ps
T796 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.557362118 Aug 19 04:38:26 PM PDT 24 Aug 19 04:38:27 PM PDT 24 86450969 ps
T797 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3249310333 Aug 19 04:38:17 PM PDT 24 Aug 19 04:38:18 PM PDT 24 15782084 ps
T798 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3687851 Aug 19 04:38:18 PM PDT 24 Aug 19 04:38:20 PM PDT 24 95077913 ps
T799 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3776479114 Aug 19 04:38:32 PM PDT 24 Aug 19 04:38:33 PM PDT 24 11577752 ps
T800 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2974842938 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:28 PM PDT 24 27257808 ps
T801 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3841922488 Aug 19 04:38:25 PM PDT 24 Aug 19 04:38:26 PM PDT 24 25734746 ps
T47 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1261957638 Aug 19 04:38:13 PM PDT 24 Aug 19 04:38:15 PM PDT 24 511853110 ps
T802 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1554331697 Aug 19 04:38:15 PM PDT 24 Aug 19 04:38:16 PM PDT 24 407525092 ps
T78 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3604910367 Aug 19 04:38:14 PM PDT 24 Aug 19 04:38:15 PM PDT 24 35612775 ps
T803 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3843308040 Aug 19 04:38:04 PM PDT 24 Aug 19 04:38:07 PM PDT 24 79463582 ps
T804 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2627917853 Aug 19 04:38:17 PM PDT 24 Aug 19 04:38:18 PM PDT 24 53993416 ps
T805 /workspace/coverage/cover_reg_top/30.gpio_intr_test.4068925487 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:30 PM PDT 24 45761082 ps
T806 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3870430792 Aug 19 04:38:35 PM PDT 24 Aug 19 04:38:36 PM PDT 24 13752020 ps
T807 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2091467680 Aug 19 04:38:16 PM PDT 24 Aug 19 04:38:18 PM PDT 24 180978663 ps
T808 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3167687556 Aug 19 04:38:40 PM PDT 24 Aug 19 04:38:40 PM PDT 24 11979363 ps
T809 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1779771729 Aug 19 04:38:17 PM PDT 24 Aug 19 04:38:18 PM PDT 24 83218875 ps
T810 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2141290409 Aug 19 04:38:24 PM PDT 24 Aug 19 04:38:24 PM PDT 24 50551642 ps
T811 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3108408299 Aug 19 04:38:30 PM PDT 24 Aug 19 04:38:31 PM PDT 24 506365112 ps
T812 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2529894479 Aug 19 04:38:05 PM PDT 24 Aug 19 04:38:06 PM PDT 24 28695217 ps
T813 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.37697868 Aug 19 04:38:26 PM PDT 24 Aug 19 04:38:27 PM PDT 24 26198319 ps
T814 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3786498401 Aug 19 04:38:28 PM PDT 24 Aug 19 04:38:29 PM PDT 24 24140499 ps
T815 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2054761088 Aug 19 04:38:15 PM PDT 24 Aug 19 04:38:16 PM PDT 24 128396331 ps
T816 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4020219607 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:31 PM PDT 24 92375307 ps
T817 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1722723545 Aug 19 04:38:35 PM PDT 24 Aug 19 04:38:37 PM PDT 24 36953889 ps
T818 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.974008834 Aug 19 04:38:12 PM PDT 24 Aug 19 04:38:13 PM PDT 24 14646119 ps
T819 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1747738968 Aug 19 04:38:04 PM PDT 24 Aug 19 04:38:04 PM PDT 24 69721854 ps
T820 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2215000651 Aug 19 04:38:20 PM PDT 24 Aug 19 04:38:22 PM PDT 24 231928799 ps
T821 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3084105906 Aug 19 04:38:10 PM PDT 24 Aug 19 04:38:10 PM PDT 24 12459729 ps
T822 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3962751559 Aug 19 04:38:24 PM PDT 24 Aug 19 04:38:26 PM PDT 24 138308659 ps
T823 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1808390906 Aug 19 04:38:17 PM PDT 24 Aug 19 04:38:18 PM PDT 24 41677037 ps
T824 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3357268998 Aug 19 04:38:15 PM PDT 24 Aug 19 04:38:16 PM PDT 24 44158205 ps
T825 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2038032744 Aug 19 04:38:39 PM PDT 24 Aug 19 04:38:40 PM PDT 24 17603289 ps
T826 /workspace/coverage/cover_reg_top/20.gpio_intr_test.4000720318 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:27 PM PDT 24 32356494 ps
T827 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2744614059 Aug 19 04:38:14 PM PDT 24 Aug 19 04:38:15 PM PDT 24 37717063 ps
T828 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1560469938 Aug 19 04:38:14 PM PDT 24 Aug 19 04:38:15 PM PDT 24 40705921 ps
T829 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.875958956 Aug 19 04:38:29 PM PDT 24 Aug 19 04:38:30 PM PDT 24 13827857 ps
T830 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2528927822 Aug 19 04:38:23 PM PDT 24 Aug 19 04:38:24 PM PDT 24 43135340 ps
T831 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4053524282 Aug 19 04:38:21 PM PDT 24 Aug 19 04:38:24 PM PDT 24 161723144 ps
T832 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3241169980 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:28 PM PDT 24 16949494 ps
T833 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3940726762 Aug 19 04:38:19 PM PDT 24 Aug 19 04:38:20 PM PDT 24 133150463 ps
T834 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1526286715 Aug 19 04:38:21 PM PDT 24 Aug 19 04:38:23 PM PDT 24 241401868 ps
T835 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.74686498 Aug 19 04:38:06 PM PDT 24 Aug 19 04:38:09 PM PDT 24 775924450 ps
T836 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2881470153 Aug 19 04:38:27 PM PDT 24 Aug 19 04:38:28 PM PDT 24 109984576 ps
T837 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2665307081 Aug 19 04:38:13 PM PDT 24 Aug 19 04:38:14 PM PDT 24 11337657 ps
T838 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1271064215 Aug 19 04:38:40 PM PDT 24 Aug 19 04:38:41 PM PDT 24 13098607 ps
T839 /workspace/coverage/cover_reg_top/9.gpio_intr_test.855297125 Aug 19 04:38:15 PM PDT 24 Aug 19 04:38:16 PM PDT 24 45978957 ps
T840 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.949299842 Aug 19 04:38:21 PM PDT 24 Aug 19 04:38:22 PM PDT 24 67700506 ps
T841 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3779726562 Aug 19 04:38:13 PM PDT 24 Aug 19 04:38:13 PM PDT 24 15232593 ps
T842 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.787305523 Aug 19 04:38:21 PM PDT 24 Aug 19 04:38:22 PM PDT 24 272571920 ps
T843 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3699542809 Aug 19 04:38:35 PM PDT 24 Aug 19 04:38:37 PM PDT 24 83893630 ps
T844 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3472153001 Aug 19 04:38:41 PM PDT 24 Aug 19 04:38:42 PM PDT 24 27706531 ps
T845 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2110294896 Aug 19 04:38:31 PM PDT 24 Aug 19 04:38:31 PM PDT 24 24248509 ps
T846 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.529926664 Aug 19 04:30:20 PM PDT 24 Aug 19 04:30:22 PM PDT 24 238958341 ps
T847 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2800048571 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:05 PM PDT 24 95817082 ps
T848 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.304070856 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:06 PM PDT 24 53622974 ps
T849 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3395301080 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:07 PM PDT 24 182599694 ps
T850 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.889950481 Aug 19 04:30:24 PM PDT 24 Aug 19 04:30:25 PM PDT 24 38630877 ps
T851 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2345356473 Aug 19 04:30:17 PM PDT 24 Aug 19 04:30:19 PM PDT 24 138447721 ps
T852 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.421845445 Aug 19 04:30:01 PM PDT 24 Aug 19 04:30:02 PM PDT 24 468437036 ps
T853 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1713108532 Aug 19 04:30:26 PM PDT 24 Aug 19 04:30:27 PM PDT 24 631280255 ps
T854 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1358543270 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:04 PM PDT 24 186959905 ps
T855 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2419704969 Aug 19 04:30:14 PM PDT 24 Aug 19 04:30:15 PM PDT 24 54791922 ps
T856 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1928342456 Aug 19 04:30:18 PM PDT 24 Aug 19 04:30:20 PM PDT 24 256071824 ps
T857 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458882146 Aug 19 04:30:12 PM PDT 24 Aug 19 04:30:13 PM PDT 24 48669017 ps
T858 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2228855982 Aug 19 04:30:29 PM PDT 24 Aug 19 04:30:30 PM PDT 24 735455014 ps
T859 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.702868921 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:57 PM PDT 24 148032903 ps
T860 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2888154257 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:01 PM PDT 24 79795292 ps
T861 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2376892835 Aug 19 04:30:11 PM PDT 24 Aug 19 04:30:13 PM PDT 24 270872329 ps
T862 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.389864328 Aug 19 04:30:10 PM PDT 24 Aug 19 04:30:11 PM PDT 24 29594712 ps
T863 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2265637693 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:10 PM PDT 24 628474128 ps
T864 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2362956810 Aug 19 04:30:22 PM PDT 24 Aug 19 04:30:24 PM PDT 24 57908705 ps
T865 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1240350103 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:06 PM PDT 24 194767335 ps
T866 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3586580867 Aug 19 04:30:14 PM PDT 24 Aug 19 04:30:16 PM PDT 24 199403788 ps
T867 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206965648 Aug 19 04:30:17 PM PDT 24 Aug 19 04:30:18 PM PDT 24 29338767 ps
T868 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3890185906 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:07 PM PDT 24 50678272 ps
T869 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1717972761 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:06 PM PDT 24 39143254 ps
T870 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1594314306 Aug 19 04:30:23 PM PDT 24 Aug 19 04:30:24 PM PDT 24 126653809 ps
T871 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.373410114 Aug 19 04:30:28 PM PDT 24 Aug 19 04:30:29 PM PDT 24 195440028 ps
T872 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1331968757 Aug 19 04:30:12 PM PDT 24 Aug 19 04:30:13 PM PDT 24 63058765 ps
T873 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4286415540 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:07 PM PDT 24 57720674 ps
T874 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126060006 Aug 19 04:30:21 PM PDT 24 Aug 19 04:30:22 PM PDT 24 33015934 ps
T875 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1232124427 Aug 19 04:30:14 PM PDT 24 Aug 19 04:30:15 PM PDT 24 102394134 ps
T876 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1258610263 Aug 19 04:29:57 PM PDT 24 Aug 19 04:29:58 PM PDT 24 157570811 ps
T877 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1821080485 Aug 19 04:30:28 PM PDT 24 Aug 19 04:30:30 PM PDT 24 220865480 ps
T878 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.890883197 Aug 19 04:29:59 PM PDT 24 Aug 19 04:30:00 PM PDT 24 263123524 ps
T879 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.666468313 Aug 19 04:30:11 PM PDT 24 Aug 19 04:30:12 PM PDT 24 90056023 ps
T880 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.463505712 Aug 19 04:30:25 PM PDT 24 Aug 19 04:30:27 PM PDT 24 69635044 ps
T881 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.282753447 Aug 19 04:30:08 PM PDT 24 Aug 19 04:30:09 PM PDT 24 213161588 ps
T882 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1589974190 Aug 19 04:30:22 PM PDT 24 Aug 19 04:30:23 PM PDT 24 35740868 ps
T883 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4102605807 Aug 19 04:30:26 PM PDT 24 Aug 19 04:30:27 PM PDT 24 70705494 ps
T884 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2633658536 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:07 PM PDT 24 138318351 ps
T885 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9477456 Aug 19 04:30:24 PM PDT 24 Aug 19 04:30:26 PM PDT 24 651501845 ps
T886 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3822385825 Aug 19 04:30:10 PM PDT 24 Aug 19 04:30:11 PM PDT 24 312419059 ps
T887 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.726160838 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:05 PM PDT 24 29455925 ps
T888 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2773911397 Aug 19 04:30:22 PM PDT 24 Aug 19 04:30:23 PM PDT 24 34986330 ps
T889 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2580049028 Aug 19 04:29:57 PM PDT 24 Aug 19 04:29:58 PM PDT 24 71456637 ps
T890 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1511409273 Aug 19 04:30:08 PM PDT 24 Aug 19 04:30:09 PM PDT 24 255639590 ps
T891 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1776653804 Aug 19 04:30:29 PM PDT 24 Aug 19 04:30:31 PM PDT 24 1154440254 ps
T892 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2534334362 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:05 PM PDT 24 54769658 ps
T893 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.38794544 Aug 19 04:30:00 PM PDT 24 Aug 19 04:30:01 PM PDT 24 306378523 ps
T894 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.877622398 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:06 PM PDT 24 49777713 ps
T895 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1751980926 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:09 PM PDT 24 43577038 ps
T896 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2672957753 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:07 PM PDT 24 154753963 ps
T897 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3295334066 Aug 19 04:30:13 PM PDT 24 Aug 19 04:30:14 PM PDT 24 193823233 ps
T898 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1481962209 Aug 19 04:30:21 PM PDT 24 Aug 19 04:30:22 PM PDT 24 173239838 ps
T899 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3340373289 Aug 19 04:30:11 PM PDT 24 Aug 19 04:30:12 PM PDT 24 310711696 ps
T900 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4234389769 Aug 19 04:30:18 PM PDT 24 Aug 19 04:30:20 PM PDT 24 183626325 ps
T901 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2839639061 Aug 19 04:30:13 PM PDT 24 Aug 19 04:30:14 PM PDT 24 87104434 ps
T902 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1318022226 Aug 19 04:30:04 PM PDT 24 Aug 19 04:30:05 PM PDT 24 64976445 ps
T903 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.145972599 Aug 19 04:30:01 PM PDT 24 Aug 19 04:30:02 PM PDT 24 27197889 ps
T904 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.240300719 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:11 PM PDT 24 40906493 ps
T905 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1725705856 Aug 19 04:30:14 PM PDT 24 Aug 19 04:30:20 PM PDT 24 59243408 ps
T906 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3548440717 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:07 PM PDT 24 166632837 ps
T907 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3269741351 Aug 19 04:30:26 PM PDT 24 Aug 19 04:30:27 PM PDT 24 61830053 ps
T908 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2665854859 Aug 19 04:30:24 PM PDT 24 Aug 19 04:30:25 PM PDT 24 196159142 ps
T909 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.639736783 Aug 19 04:30:08 PM PDT 24 Aug 19 04:30:10 PM PDT 24 64574487 ps
T910 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1077003682 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:04 PM PDT 24 56654661 ps
T911 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735468898 Aug 19 04:30:27 PM PDT 24 Aug 19 04:30:28 PM PDT 24 39194085 ps
T912 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1653132773 Aug 19 04:30:12 PM PDT 24 Aug 19 04:30:12 PM PDT 24 26649530 ps
T913 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1040477323 Aug 19 04:30:15 PM PDT 24 Aug 19 04:30:16 PM PDT 24 299740902 ps
T914 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3170869188 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:04 PM PDT 24 30513780 ps
T915 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.274720361 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:04 PM PDT 24 43423703 ps
T916 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.946891750 Aug 19 04:29:54 PM PDT 24 Aug 19 04:29:55 PM PDT 24 211191626 ps
T917 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2063988187 Aug 19 04:30:18 PM PDT 24 Aug 19 04:30:19 PM PDT 24 266723956 ps
T918 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1455446000 Aug 19 04:29:57 PM PDT 24 Aug 19 04:29:58 PM PDT 24 166737729 ps
T919 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2500892485 Aug 19 04:30:15 PM PDT 24 Aug 19 04:30:16 PM PDT 24 361905229 ps
T920 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1932103144 Aug 19 04:30:05 PM PDT 24 Aug 19 04:30:06 PM PDT 24 34961877 ps
T921 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.720932794 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:08 PM PDT 24 43135196 ps
T922 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2715711297 Aug 19 04:29:56 PM PDT 24 Aug 19 04:29:57 PM PDT 24 35570364 ps
T923 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.471795139 Aug 19 04:30:24 PM PDT 24 Aug 19 04:30:25 PM PDT 24 65969547 ps
T924 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1943222276 Aug 19 04:30:19 PM PDT 24 Aug 19 04:30:20 PM PDT 24 168550503 ps
T925 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2334512111 Aug 19 04:30:31 PM PDT 24 Aug 19 04:30:33 PM PDT 24 48063709 ps
T926 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2469101895 Aug 19 04:30:07 PM PDT 24 Aug 19 04:30:08 PM PDT 24 46883157 ps
T927 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1417182876 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:07 PM PDT 24 151238856 ps
T928 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4288213673 Aug 19 04:30:25 PM PDT 24 Aug 19 04:30:26 PM PDT 24 59258631 ps
T929 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3354596670 Aug 19 04:30:11 PM PDT 24 Aug 19 04:30:12 PM PDT 24 54362609 ps
T930 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1361582959 Aug 19 04:30:24 PM PDT 24 Aug 19 04:30:25 PM PDT 24 66488421 ps
T931 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946915953 Aug 19 04:30:26 PM PDT 24 Aug 19 04:30:27 PM PDT 24 333142363 ps
T932 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4242097135 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:07 PM PDT 24 87745991 ps
T933 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3560019476 Aug 19 04:30:06 PM PDT 24 Aug 19 04:30:08 PM PDT 24 101032706 ps
T934 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3744132523 Aug 19 04:30:25 PM PDT 24 Aug 19 04:30:26 PM PDT 24 84623642 ps
T935 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2438774115 Aug 19 04:30:14 PM PDT 24 Aug 19 04:30:15 PM PDT 24 45537598 ps
T936 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.872814564 Aug 19 04:30:01 PM PDT 24 Aug 19 04:30:03 PM PDT 24 177499999 ps
T937 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4051229795 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:10 PM PDT 24 73329929 ps
T938 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.757238595 Aug 19 04:30:27 PM PDT 24 Aug 19 04:30:28 PM PDT 24 45627267 ps
T939 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2671942572 Aug 19 04:30:17 PM PDT 24 Aug 19 04:30:18 PM PDT 24 43747525 ps
T940 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1025235224 Aug 19 04:30:09 PM PDT 24 Aug 19 04:30:10 PM PDT 24 86768120 ps
T941 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3435383815 Aug 19 04:29:55 PM PDT 24 Aug 19 04:29:56 PM PDT 24 135899266 ps
T942 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2803454931 Aug 19 04:30:25 PM PDT 24 Aug 19 04:30:26 PM PDT 24 429005762 ps
T943 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1447102069 Aug 19 04:30:33 PM PDT 24 Aug 19 04:30:34 PM PDT 24 85455638 ps
T944 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1928877154 Aug 19 04:30:03 PM PDT 24 Aug 19 04:30:09 PM PDT 24 636347232 ps
T945 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2073407630 Aug 19 04:30:10 PM PDT 24 Aug 19 04:30:12 PM PDT 24 221578033 ps

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3776784229
Short name T1
Test name
Test status
Simulation time 4284031944 ps
CPU time 5.86 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:56 PM PDT 24
Peak memory 198284 kb
Host smart-d7ddd55a-49ab-4a28-9dfb-a791c9777dbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776784229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3776784229
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1514336508
Short name T90
Test name
Test status
Simulation time 184323229 ps
CPU time 2.17 seconds
Started Aug 19 05:23:14 PM PDT 24
Finished Aug 19 05:23:16 PM PDT 24
Peak memory 196228 kb
Host smart-9753b2e0-7f67-462d-a510-5043dbcf5cb8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514336508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1514336508
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1151301707
Short name T11
Test name
Test status
Simulation time 970491652 ps
CPU time 18.87 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:35 PM PDT 24
Peak memory 197992 kb
Host smart-1c1d086e-8371-496f-b75f-1de2617059dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1151301707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1151301707
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3648755964
Short name T36
Test name
Test status
Simulation time 251999799 ps
CPU time 0.9 seconds
Started Aug 19 05:22:46 PM PDT 24
Finished Aug 19 05:22:47 PM PDT 24
Peak memory 213932 kb
Host smart-35c9b532-bf41-4980-8afc-0cdfd25a40c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648755964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3648755964
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.478452329
Short name T70
Test name
Test status
Simulation time 193530122 ps
CPU time 0.76 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:38:04 PM PDT 24
Peak memory 197052 kb
Host smart-367e4bdf-0894-4f1e-8e7a-44480544502e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478452329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.478452329
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.377826225
Short name T44
Test name
Test status
Simulation time 688708575 ps
CPU time 1.4 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 198260 kb
Host smart-50318310-787f-45b3-b108-d688426511f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377826225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.377826225
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.678801959
Short name T137
Test name
Test status
Simulation time 19948872 ps
CPU time 0.56 seconds
Started Aug 19 05:22:10 PM PDT 24
Finished Aug 19 05:22:10 PM PDT 24
Peak memory 194776 kb
Host smart-fbfd01a8-225b-400b-8c35-ed8403ece51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678801959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.678801959
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1301845625
Short name T81
Test name
Test status
Simulation time 34378158 ps
CPU time 0.85 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 196796 kb
Host smart-e0219db6-045d-4f57-9c17-93cae0d6bc7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301845625 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1301845625
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1727265289
Short name T35
Test name
Test status
Simulation time 253193702 ps
CPU time 1.08 seconds
Started Aug 19 04:38:36 PM PDT 24
Finished Aug 19 04:38:37 PM PDT 24
Peak memory 198076 kb
Host smart-5d0aaab5-7a17-4f52-b571-f7c708259f86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727265289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1727265289
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3608078760
Short name T772
Test name
Test status
Simulation time 62219149 ps
CPU time 0.64 seconds
Started Aug 19 04:38:23 PM PDT 24
Finished Aug 19 04:38:23 PM PDT 24
Peak memory 195984 kb
Host smart-eadf50b3-2170-47c9-a684-05a3558f995f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608078760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3608078760
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3835546573
Short name T85
Test name
Test status
Simulation time 151850145 ps
CPU time 2.16 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:38:08 PM PDT 24
Peak memory 198428 kb
Host smart-f8b4e81d-4a09-47c0-bd4c-a0a4632a3112
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835546573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3835546573
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1747738968
Short name T819
Test name
Test status
Simulation time 69721854 ps
CPU time 0.66 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:38:04 PM PDT 24
Peak memory 196044 kb
Host smart-753c9173-7711-4d61-bc43-bdc8ef3eaaaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747738968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1747738968
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2054761088
Short name T815
Test name
Test status
Simulation time 128396331 ps
CPU time 0.87 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 198428 kb
Host smart-d4d8c66d-1c19-4536-a37e-cb23157e93f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054761088 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2054761088
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1808390906
Short name T823
Test name
Test status
Simulation time 41677037 ps
CPU time 0.64 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 194916 kb
Host smart-a175a022-54ee-4aae-9a9c-ea82edcdcf73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808390906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1808390906
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2851083582
Short name T727
Test name
Test status
Simulation time 65805121 ps
CPU time 0.57 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:28 PM PDT 24
Peak memory 194308 kb
Host smart-9342a20d-d1fe-43e4-87da-e4736a2ac580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851083582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2851083582
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1322979079
Short name T777
Test name
Test status
Simulation time 12200804 ps
CPU time 0.61 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:38:20 PM PDT 24
Peak memory 195208 kb
Host smart-6caf2e71-3c3c-4ce0-aaad-e6ea19fe61ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322979079 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1322979079
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2853616405
Short name T743
Test name
Test status
Simulation time 130296888 ps
CPU time 2.22 seconds
Started Aug 19 04:38:20 PM PDT 24
Finished Aug 19 04:38:23 PM PDT 24
Peak memory 198580 kb
Host smart-6fd1906b-852f-4002-ad7b-073fcca8194c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853616405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2853616405
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2848595793
Short name T33
Test name
Test status
Simulation time 85491348 ps
CPU time 1.11 seconds
Started Aug 19 04:38:08 PM PDT 24
Finished Aug 19 04:38:09 PM PDT 24
Peak memory 198552 kb
Host smart-bfb30d95-af59-42fa-892a-7632a093d795
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848595793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2848595793
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3843308040
Short name T803
Test name
Test status
Simulation time 79463582 ps
CPU time 2.96 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:38:07 PM PDT 24
Peak memory 197672 kb
Host smart-28f87c3a-1a60-498e-b2d3-82de9c89d567
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843308040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3843308040
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.787305523
Short name T842
Test name
Test status
Simulation time 272571920 ps
CPU time 0.64 seconds
Started Aug 19 04:38:21 PM PDT 24
Finished Aug 19 04:38:22 PM PDT 24
Peak memory 195972 kb
Host smart-790e74e1-60f3-436d-8f86-8fffec960648
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787305523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.787305523
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2973080264
Short name T744
Test name
Test status
Simulation time 55662736 ps
CPU time 1.19 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:38:03 PM PDT 24
Peak memory 198580 kb
Host smart-fc2fbe8f-0305-45d5-92b3-54dae7651443
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973080264 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2973080264
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1111828894
Short name T76
Test name
Test status
Simulation time 39912175 ps
CPU time 0.58 seconds
Started Aug 19 04:38:07 PM PDT 24
Finished Aug 19 04:38:08 PM PDT 24
Peak memory 195216 kb
Host smart-9907ae53-ef72-4446-b44d-349bca3908ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111828894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1111828894
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1997099499
Short name T716
Test name
Test status
Simulation time 11904645 ps
CPU time 0.61 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:38:07 PM PDT 24
Peak memory 194248 kb
Host smart-9237a956-8333-4cba-b784-16e5e68277a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997099499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1997099499
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2529894479
Short name T812
Test name
Test status
Simulation time 28695217 ps
CPU time 0.72 seconds
Started Aug 19 04:38:05 PM PDT 24
Finished Aug 19 04:38:06 PM PDT 24
Peak memory 196376 kb
Host smart-933333e2-6a2e-495f-a2eb-f0abcc481538
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529894479 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2529894479
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2923316902
Short name T763
Test name
Test status
Simulation time 586497666 ps
CPU time 3.21 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:38:22 PM PDT 24
Peak memory 198588 kb
Host smart-c23d3382-ea2a-411e-9b3a-aef6bbfbe774
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923316902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2923316902
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1651228570
Short name T32
Test name
Test status
Simulation time 290362770 ps
CPU time 1.11 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:38:07 PM PDT 24
Peak memory 198464 kb
Host smart-3ade28c7-263b-46f1-b903-e51b3f395759
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651228570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1651228570
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3447858295
Short name T749
Test name
Test status
Simulation time 18265404 ps
CPU time 0.66 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 197404 kb
Host smart-959e053b-0803-44ac-86fd-6675e8428c2c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447858295 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3447858295
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2770583783
Short name T73
Test name
Test status
Simulation time 27498299 ps
CPU time 0.57 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 194072 kb
Host smart-c7b92f25-3854-49d6-8f21-94ca57edda69
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770583783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2770583783
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1781704630
Short name T786
Test name
Test status
Simulation time 17301518 ps
CPU time 0.59 seconds
Started Aug 19 04:38:18 PM PDT 24
Finished Aug 19 04:38:19 PM PDT 24
Peak memory 194208 kb
Host smart-c9e5aed3-96d4-4b23-b63f-de6086eaad00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781704630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1781704630
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2528927822
Short name T830
Test name
Test status
Simulation time 43135340 ps
CPU time 0.87 seconds
Started Aug 19 04:38:23 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 196856 kb
Host smart-22a68f9b-4438-405c-b3be-61956381c068
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528927822 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2528927822
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.534118865
Short name T766
Test name
Test status
Simulation time 94499611 ps
CPU time 2.45 seconds
Started Aug 19 04:38:21 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 198544 kb
Host smart-6b99e529-3711-4406-a61e-090bb9a514f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534118865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.534118865
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1722723545
Short name T817
Test name
Test status
Simulation time 36953889 ps
CPU time 1.44 seconds
Started Aug 19 04:38:35 PM PDT 24
Finished Aug 19 04:38:37 PM PDT 24
Peak memory 198576 kb
Host smart-501d1b63-4f87-4d1e-a13a-2eabc7cefb31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722723545 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1722723545
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2684220799
Short name T77
Test name
Test status
Simulation time 89968389 ps
CPU time 0.59 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 196040 kb
Host smart-4b8d5d41-8b40-4c9d-be6e-79d573eb70de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684220799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2684220799
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1779771729
Short name T809
Test name
Test status
Simulation time 83218875 ps
CPU time 0.56 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 194160 kb
Host smart-bc9dee47-1876-429a-b9a8-c6e6040ebc99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779771729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1779771729
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2881470153
Short name T836
Test name
Test status
Simulation time 109984576 ps
CPU time 0.72 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:28 PM PDT 24
Peak memory 197316 kb
Host smart-0c3ddd62-5f2b-4287-8ba0-1e21bb4df0c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881470153 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2881470153
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2961534759
Short name T720
Test name
Test status
Simulation time 48542632 ps
CPU time 2.35 seconds
Started Aug 19 04:38:16 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 198616 kb
Host smart-64235ea4-e4fc-47e5-b953-25b213f725d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961534759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2961534759
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1554331697
Short name T802
Test name
Test status
Simulation time 407525092 ps
CPU time 0.87 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 198292 kb
Host smart-ac764495-1d8f-4042-b9ef-0a2e4d3c9e1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554331697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1554331697
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3249310333
Short name T797
Test name
Test status
Simulation time 15782084 ps
CPU time 0.67 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 197232 kb
Host smart-7f3c6061-f440-425b-9de1-550ccd7aafcb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249310333 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3249310333
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4024705163
Short name T759
Test name
Test status
Simulation time 13353285 ps
CPU time 0.62 seconds
Started Aug 19 04:38:24 PM PDT 24
Finished Aug 19 04:38:25 PM PDT 24
Peak memory 195220 kb
Host smart-756b263f-c58b-414d-9871-f8f36b7a9ae5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024705163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4024705163
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1567519085
Short name T717
Test name
Test status
Simulation time 14211791 ps
CPU time 0.67 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:38:17 PM PDT 24
Peak memory 194260 kb
Host smart-2c8ba3ed-4736-4b8b-ac1f-b921c824314e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567519085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1567519085
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2027426329
Short name T790
Test name
Test status
Simulation time 80268758 ps
CPU time 0.62 seconds
Started Aug 19 04:38:12 PM PDT 24
Finished Aug 19 04:38:13 PM PDT 24
Peak memory 195096 kb
Host smart-8520ebcb-aa47-4698-af62-fdfc5f382335
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027426329 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2027426329
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3749068838
Short name T760
Test name
Test status
Simulation time 83097381 ps
CPU time 1.79 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 198584 kb
Host smart-abb5aaa4-d1cd-4e81-8003-59aad492ebac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749068838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3749068838
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3786498401
Short name T814
Test name
Test status
Simulation time 24140499 ps
CPU time 1.09 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 198252 kb
Host smart-0469042b-bcb5-4b74-b2e2-4cdff33a5449
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786498401 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3786498401
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4062671011
Short name T87
Test name
Test status
Simulation time 17767891 ps
CPU time 0.62 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 195716 kb
Host smart-9f8e0b00-bf8c-4cfd-98e7-fb7a2225e1f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062671011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4062671011
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1498503103
Short name T724
Test name
Test status
Simulation time 14465184 ps
CPU time 0.62 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 194128 kb
Host smart-4c93040c-95dd-42b3-a9e0-d0b134793bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498503103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1498503103
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3699542809
Short name T843
Test name
Test status
Simulation time 83893630 ps
CPU time 2.16 seconds
Started Aug 19 04:38:35 PM PDT 24
Finished Aug 19 04:38:37 PM PDT 24
Peak memory 198596 kb
Host smart-3e864c78-889b-4a8e-a6d0-649da52e6a30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699542809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3699542809
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2650146363
Short name T89
Test name
Test status
Simulation time 296023208 ps
CPU time 1.12 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:28 PM PDT 24
Peak memory 198536 kb
Host smart-4ce813f5-a5f5-40a2-a695-47f8b5b07ef2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650146363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2650146363
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1718923517
Short name T726
Test name
Test status
Simulation time 52852524 ps
CPU time 1.28 seconds
Started Aug 19 04:38:30 PM PDT 24
Finished Aug 19 04:38:31 PM PDT 24
Peak memory 198600 kb
Host smart-c20d6782-2627-4151-8ca2-5628142e4298
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718923517 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1718923517
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3296576456
Short name T739
Test name
Test status
Simulation time 14920757 ps
CPU time 0.62 seconds
Started Aug 19 04:38:16 PM PDT 24
Finished Aug 19 04:38:17 PM PDT 24
Peak memory 195136 kb
Host smart-c6a096cd-d20f-4584-9a3e-692b7d1a2091
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296576456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3296576456
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2986439486
Short name T723
Test name
Test status
Simulation time 13925754 ps
CPU time 0.61 seconds
Started Aug 19 04:38:36 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 194088 kb
Host smart-1d316544-ba9c-470e-8c27-7a8f778a397f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986439486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2986439486
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1127668087
Short name T84
Test name
Test status
Simulation time 32770099 ps
CPU time 0.73 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 196608 kb
Host smart-a65624d9-e6eb-4e80-b19e-2ce58619dcea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127668087 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1127668087
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2862453952
Short name T728
Test name
Test status
Simulation time 89683728 ps
CPU time 1.66 seconds
Started Aug 19 04:38:36 PM PDT 24
Finished Aug 19 04:38:37 PM PDT 24
Peak memory 198524 kb
Host smart-f6fdea1d-4a91-4261-8faf-8661b1adfe9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862453952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2862453952
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4273543681
Short name T34
Test name
Test status
Simulation time 491457600 ps
CPU time 1.42 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 198492 kb
Host smart-9a705f1b-4303-4938-aa43-114688bdf97f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273543681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4273543681
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.98738147
Short name T767
Test name
Test status
Simulation time 27160055 ps
CPU time 1.11 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:28 PM PDT 24
Peak memory 198644 kb
Host smart-46f35dc4-436a-453e-af3e-9e843bd9ce22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98738147 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.98738147
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.557362118
Short name T796
Test name
Test status
Simulation time 86450969 ps
CPU time 0.59 seconds
Started Aug 19 04:38:26 PM PDT 24
Finished Aug 19 04:38:27 PM PDT 24
Peak memory 194972 kb
Host smart-e60fd825-071d-4828-8616-567d4e3e4f88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557362118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.557362118
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.397182029
Short name T761
Test name
Test status
Simulation time 33871264 ps
CPU time 0.56 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:38:20 PM PDT 24
Peak memory 194244 kb
Host smart-80d79840-55b0-43e0-a208-dafc69bef0f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397182029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.397182029
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2179198622
Short name T79
Test name
Test status
Simulation time 21140086 ps
CPU time 0.67 seconds
Started Aug 19 04:38:35 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 194948 kb
Host smart-db1e5533-ef5d-4ba0-a013-36121e0e0992
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179198622 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2179198622
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1622229547
Short name T791
Test name
Test status
Simulation time 330349056 ps
CPU time 2.83 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 198576 kb
Host smart-6e7120ab-5b38-465b-8452-dece9022f9d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622229547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1622229547
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2215000651
Short name T820
Test name
Test status
Simulation time 231928799 ps
CPU time 1.35 seconds
Started Aug 19 04:38:20 PM PDT 24
Finished Aug 19 04:38:22 PM PDT 24
Peak memory 198556 kb
Host smart-616539e3-c3c3-434e-bc7f-6e1b275891fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215000651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2215000651
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3252487534
Short name T792
Test name
Test status
Simulation time 22787350 ps
CPU time 0.96 seconds
Started Aug 19 04:38:38 PM PDT 24
Finished Aug 19 04:38:39 PM PDT 24
Peak memory 198268 kb
Host smart-657a19f5-d0f0-47e2-b6fc-067fe65f1731
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252487534 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3252487534
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3870430792
Short name T806
Test name
Test status
Simulation time 13752020 ps
CPU time 0.58 seconds
Started Aug 19 04:38:35 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 193636 kb
Host smart-f2a60b60-6a2f-463a-bdc4-718fb7e01f1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870430792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3870430792
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2599879421
Short name T756
Test name
Test status
Simulation time 12444901 ps
CPU time 0.55 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:38:19 PM PDT 24
Peak memory 194192 kb
Host smart-1e528b14-61bc-4e5e-b443-8c4c3130b52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599879421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2599879421
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2763432461
Short name T789
Test name
Test status
Simulation time 13295608 ps
CPU time 0.62 seconds
Started Aug 19 04:38:36 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 195148 kb
Host smart-ab641128-9dd2-49d0-a4a2-b3d0d5aa582f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763432461 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2763432461
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1102016782
Short name T769
Test name
Test status
Simulation time 228329383 ps
CPU time 1.59 seconds
Started Aug 19 04:38:16 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 198620 kb
Host smart-9413abb5-66a9-491c-9ad9-8da053dcf85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102016782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1102016782
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3729688911
Short name T43
Test name
Test status
Simulation time 121960728 ps
CPU time 1.38 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 198480 kb
Host smart-34cd4fa9-f55d-44b8-ba86-2e7a57d0c57b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729688911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3729688911
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2690788012
Short name T751
Test name
Test status
Simulation time 60931940 ps
CPU time 1.61 seconds
Started Aug 19 04:38:35 PM PDT 24
Finished Aug 19 04:38:37 PM PDT 24
Peak memory 198488 kb
Host smart-2ac7c297-294e-499a-bb30-d9b3e586937d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690788012 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2690788012
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2371841243
Short name T71
Test name
Test status
Simulation time 14153138 ps
CPU time 0.61 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 193788 kb
Host smart-9525b067-7539-4cee-84c6-3a62041b4edf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371841243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2371841243
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1874147724
Short name T747
Test name
Test status
Simulation time 14817273 ps
CPU time 0.58 seconds
Started Aug 19 04:38:16 PM PDT 24
Finished Aug 19 04:38:17 PM PDT 24
Peak memory 194880 kb
Host smart-ec55054d-c17f-4043-abfc-be7c7b810115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874147724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1874147724
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3203071242
Short name T793
Test name
Test status
Simulation time 26617820 ps
CPU time 0.72 seconds
Started Aug 19 04:38:36 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 196952 kb
Host smart-88410dad-1916-4bf0-9ee4-c259c997c45b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203071242 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3203071242
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3941975520
Short name T765
Test name
Test status
Simulation time 72776677 ps
CPU time 1.88 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 198668 kb
Host smart-58016af6-071a-4442-8516-3f1b1bbb0f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941975520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3941975520
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2251606915
Short name T31
Test name
Test status
Simulation time 423163056 ps
CPU time 1.44 seconds
Started Aug 19 04:38:38 PM PDT 24
Finished Aug 19 04:38:39 PM PDT 24
Peak memory 198352 kb
Host smart-706093a4-b632-4553-8d37-98f05298af43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251606915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2251606915
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.37697868
Short name T813
Test name
Test status
Simulation time 26198319 ps
CPU time 0.77 seconds
Started Aug 19 04:38:26 PM PDT 24
Finished Aug 19 04:38:27 PM PDT 24
Peak memory 198368 kb
Host smart-94851e68-969c-407a-a1a1-c5fa00167378
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37697868 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.37697868
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1969732166
Short name T75
Test name
Test status
Simulation time 11322033 ps
CPU time 0.57 seconds
Started Aug 19 04:38:36 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 194968 kb
Host smart-3d4abf40-e655-47fb-b80d-31f5a5faaf45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969732166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1969732166
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3776479114
Short name T799
Test name
Test status
Simulation time 11577752 ps
CPU time 0.59 seconds
Started Aug 19 04:38:32 PM PDT 24
Finished Aug 19 04:38:33 PM PDT 24
Peak memory 194316 kb
Host smart-2524ebcf-43c2-410f-a57e-438f9f333825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776479114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3776479114
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2968078151
Short name T80
Test name
Test status
Simulation time 35078672 ps
CPU time 0.76 seconds
Started Aug 19 04:38:37 PM PDT 24
Finished Aug 19 04:38:37 PM PDT 24
Peak memory 196588 kb
Host smart-ca9be838-2873-416d-b969-2ad48b4a636f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968078151 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2968078151
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2809507518
Short name T752
Test name
Test status
Simulation time 727455807 ps
CPU time 2.82 seconds
Started Aug 19 04:38:31 PM PDT 24
Finished Aug 19 04:38:34 PM PDT 24
Peak memory 198620 kb
Host smart-10dd32ea-7651-4329-860b-b725bd5f02d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809507518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2809507518
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3108408299
Short name T811
Test name
Test status
Simulation time 506365112 ps
CPU time 1.38 seconds
Started Aug 19 04:38:30 PM PDT 24
Finished Aug 19 04:38:31 PM PDT 24
Peak memory 198540 kb
Host smart-acf4c1f9-001f-4e9d-800d-bbcf26c55a81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108408299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3108408299
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2271954821
Short name T721
Test name
Test status
Simulation time 70744513 ps
CPU time 1.05 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 198692 kb
Host smart-4b3f461b-72ad-45a0-850d-49838db5eee7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271954821 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2271954821
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.530139705
Short name T773
Test name
Test status
Simulation time 14254786 ps
CPU time 0.64 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 195244 kb
Host smart-58d25e49-ed71-407f-b0a8-5124f9af224b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530139705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.530139705
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1313657243
Short name T778
Test name
Test status
Simulation time 62974735 ps
CPU time 0.62 seconds
Started Aug 19 04:38:41 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 194156 kb
Host smart-a48afc1b-4584-41aa-bb2c-73d12263d406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313657243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1313657243
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.875958956
Short name T829
Test name
Test status
Simulation time 13827857 ps
CPU time 0.64 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 195252 kb
Host smart-9a32580a-585d-43c9-9b0e-c4e87712ed31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875958956 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.875958956
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1997481618
Short name T757
Test name
Test status
Simulation time 55008012 ps
CPU time 1.37 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 198576 kb
Host smart-69b4b2c2-e616-4870-9d09-a7fc1675b414
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997481618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1997481618
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1892131851
Short name T775
Test name
Test status
Simulation time 439973189 ps
CPU time 1.13 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 198528 kb
Host smart-c6d20e7f-cedb-47f5-8504-033ada164102
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892131851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1892131851
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.4246808474
Short name T66
Test name
Test status
Simulation time 34145279 ps
CPU time 0.65 seconds
Started Aug 19 04:38:11 PM PDT 24
Finished Aug 19 04:38:12 PM PDT 24
Peak memory 194904 kb
Host smart-aed1c282-4fa8-4a8f-b376-96a0c28b4a7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246808474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.4246808474
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.283106097
Short name T86
Test name
Test status
Simulation time 1520942440 ps
CPU time 2.24 seconds
Started Aug 19 04:38:25 PM PDT 24
Finished Aug 19 04:38:27 PM PDT 24
Peak memory 197380 kb
Host smart-dd09330d-cd6c-43c3-b7c8-78ab55ba35ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283106097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.283106097
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3579507243
Short name T67
Test name
Test status
Simulation time 172769342 ps
CPU time 0.58 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 194728 kb
Host smart-d5073181-3d0f-472a-97d6-b5a301778cc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579507243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3579507243
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.577695102
Short name T783
Test name
Test status
Simulation time 93425851 ps
CPU time 0.7 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 197840 kb
Host smart-742bc121-849d-4fc9-ba81-f454e1dfb959
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577695102 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.577695102
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4114086277
Short name T750
Test name
Test status
Simulation time 56508002 ps
CPU time 0.62 seconds
Started Aug 19 04:38:26 PM PDT 24
Finished Aug 19 04:38:26 PM PDT 24
Peak memory 195280 kb
Host smart-824870a5-14da-4d66-96f4-e91bf335a5e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114086277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.4114086277
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2003953289
Short name T753
Test name
Test status
Simulation time 25122165 ps
CPU time 0.61 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 194960 kb
Host smart-3b94a51b-c37b-497c-9ea3-91edc825ea98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003953289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2003953289
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.486966391
Short name T74
Test name
Test status
Simulation time 30618061 ps
CPU time 0.62 seconds
Started Aug 19 04:38:32 PM PDT 24
Finished Aug 19 04:38:32 PM PDT 24
Peak memory 195200 kb
Host smart-e37e57f8-e844-4dc6-97d4-979471ddc886
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486966391 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.486966391
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2139431689
Short name T782
Test name
Test status
Simulation time 321193083 ps
CPU time 0.93 seconds
Started Aug 19 04:38:08 PM PDT 24
Finished Aug 19 04:38:09 PM PDT 24
Peak memory 198432 kb
Host smart-24cd63d5-b037-4daf-8122-aa723e17fda8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139431689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2139431689
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3855767440
Short name T42
Test name
Test status
Simulation time 225245740 ps
CPU time 1.42 seconds
Started Aug 19 04:38:10 PM PDT 24
Finished Aug 19 04:38:11 PM PDT 24
Peak memory 198592 kb
Host smart-4f0f34a4-371e-42f8-a8f6-72bc47446dcc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855767440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3855767440
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4000720318
Short name T826
Test name
Test status
Simulation time 32356494 ps
CPU time 0.57 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:27 PM PDT 24
Peak memory 194216 kb
Host smart-a8f38ef1-0eac-474d-a1a2-8b896e70e082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000720318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4000720318
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2483045942
Short name T719
Test name
Test status
Simulation time 30493345 ps
CPU time 0.58 seconds
Started Aug 19 04:38:30 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 194192 kb
Host smart-3b168291-f10d-48a1-b93c-05d41cd7f2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483045942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2483045942
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4134103689
Short name T758
Test name
Test status
Simulation time 33786267 ps
CPU time 0.61 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 194952 kb
Host smart-e2fe208d-5506-49f4-b3fe-a65dded7c83b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134103689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4134103689
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3841922488
Short name T801
Test name
Test status
Simulation time 25734746 ps
CPU time 0.55 seconds
Started Aug 19 04:38:25 PM PDT 24
Finished Aug 19 04:38:26 PM PDT 24
Peak memory 194216 kb
Host smart-1c2fc804-1bee-4268-8af6-37016190e273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841922488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3841922488
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3565294642
Short name T770
Test name
Test status
Simulation time 14122959 ps
CPU time 0.56 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 194184 kb
Host smart-3e8009cb-de85-406a-9492-f7996f8004cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565294642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3565294642
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2780304912
Short name T776
Test name
Test status
Simulation time 17513472 ps
CPU time 0.62 seconds
Started Aug 19 04:38:31 PM PDT 24
Finished Aug 19 04:38:31 PM PDT 24
Peak memory 194296 kb
Host smart-7588d63c-07cd-460e-9193-44d10eb4e12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780304912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2780304912
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.4277244501
Short name T784
Test name
Test status
Simulation time 40635381 ps
CPU time 0.61 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 194252 kb
Host smart-6f88d5c3-3236-47df-b62d-898a13e0c377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277244501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.4277244501
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2110294896
Short name T845
Test name
Test status
Simulation time 24248509 ps
CPU time 0.56 seconds
Started Aug 19 04:38:31 PM PDT 24
Finished Aug 19 04:38:31 PM PDT 24
Peak memory 194208 kb
Host smart-662a26e0-b17d-48a8-a2c0-6d7d4c8d6c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110294896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2110294896
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3241169980
Short name T832
Test name
Test status
Simulation time 16949494 ps
CPU time 0.53 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:28 PM PDT 24
Peak memory 194184 kb
Host smart-9a355fb6-41b6-4890-8d70-88a0d2e89ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241169980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3241169980
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2099021461
Short name T737
Test name
Test status
Simulation time 33159694 ps
CPU time 0.55 seconds
Started Aug 19 04:38:32 PM PDT 24
Finished Aug 19 04:38:33 PM PDT 24
Peak memory 194184 kb
Host smart-a793e82c-29c3-46d1-83ba-59a6919c86a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099021461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2099021461
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.949299842
Short name T840
Test name
Test status
Simulation time 67700506 ps
CPU time 0.65 seconds
Started Aug 19 04:38:21 PM PDT 24
Finished Aug 19 04:38:22 PM PDT 24
Peak memory 195668 kb
Host smart-f1b3f4e9-f48f-42d6-8d01-b4fff1dfdc8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949299842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.949299842
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3687851
Short name T798
Test name
Test status
Simulation time 95077913 ps
CPU time 1.47 seconds
Started Aug 19 04:38:18 PM PDT 24
Finished Aug 19 04:38:20 PM PDT 24
Peak memory 197520 kb
Host smart-9a888875-d981-401c-86f9-1e31125a0918
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3687851
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1659754643
Short name T734
Test name
Test status
Simulation time 16440460 ps
CPU time 0.59 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 195128 kb
Host smart-30b1ee6a-82e8-4caa-bfec-92abe52dab6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659754643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1659754643
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2627917853
Short name T804
Test name
Test status
Simulation time 53993416 ps
CPU time 0.95 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 198316 kb
Host smart-5434582f-8e99-48d5-925a-f1aa1ccb8393
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627917853 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2627917853
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2665307081
Short name T837
Test name
Test status
Simulation time 11337657 ps
CPU time 0.58 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 195196 kb
Host smart-154f0c23-a823-4d2d-b7af-8a2fd47fdc59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665307081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2665307081
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3779726562
Short name T841
Test name
Test status
Simulation time 15232593 ps
CPU time 0.59 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:13 PM PDT 24
Peak memory 194232 kb
Host smart-186ce29c-a659-468c-a59e-b933cb78dc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779726562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3779726562
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3789744562
Short name T72
Test name
Test status
Simulation time 12378877 ps
CPU time 0.65 seconds
Started Aug 19 04:38:11 PM PDT 24
Finished Aug 19 04:38:12 PM PDT 24
Peak memory 195220 kb
Host smart-96f2e303-2e6f-4b1c-b5b2-b9c1aa631523
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789744562 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3789744562
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3710482606
Short name T748
Test name
Test status
Simulation time 135370499 ps
CPU time 2.2 seconds
Started Aug 19 04:38:25 PM PDT 24
Finished Aug 19 04:38:27 PM PDT 24
Peak memory 198648 kb
Host smart-c064c234-a966-47e6-babc-140c424d8a76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710482606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3710482606
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1261957638
Short name T47
Test name
Test status
Simulation time 511853110 ps
CPU time 1.07 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 198496 kb
Host smart-a3ecaa3a-b2cc-4bcc-b170-7ef6c3721dab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261957638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1261957638
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.4068925487
Short name T805
Test name
Test status
Simulation time 45761082 ps
CPU time 0.64 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 194276 kb
Host smart-04b4e50b-4438-4a02-b69c-7ce2f71643e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068925487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.4068925487
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3167687556
Short name T808
Test name
Test status
Simulation time 11979363 ps
CPU time 0.55 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:40 PM PDT 24
Peak memory 194168 kb
Host smart-d89af6ef-3c64-4696-935e-280327401a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167687556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3167687556
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3472153001
Short name T844
Test name
Test status
Simulation time 27706531 ps
CPU time 0.59 seconds
Started Aug 19 04:38:41 PM PDT 24
Finished Aug 19 04:38:42 PM PDT 24
Peak memory 194212 kb
Host smart-0c8e3fe5-5460-4c1b-b09a-27df87579c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472153001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3472153001
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3426232155
Short name T722
Test name
Test status
Simulation time 19631108 ps
CPU time 0.59 seconds
Started Aug 19 04:38:42 PM PDT 24
Finished Aug 19 04:38:43 PM PDT 24
Peak memory 194900 kb
Host smart-c7477c90-b770-4fc1-9961-bca7dce8994a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426232155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3426232155
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3104879367
Short name T729
Test name
Test status
Simulation time 19948040 ps
CPU time 0.61 seconds
Started Aug 19 04:38:38 PM PDT 24
Finished Aug 19 04:38:39 PM PDT 24
Peak memory 194244 kb
Host smart-592c0bca-27f9-40f3-a7fc-8b3bf87fb067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104879367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3104879367
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1200797151
Short name T754
Test name
Test status
Simulation time 118756766 ps
CPU time 0.55 seconds
Started Aug 19 04:38:37 PM PDT 24
Finished Aug 19 04:38:37 PM PDT 24
Peak memory 194172 kb
Host smart-8f9def1f-2583-4daa-961e-cfb371712b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200797151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1200797151
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2135189281
Short name T780
Test name
Test status
Simulation time 22677765 ps
CPU time 0.54 seconds
Started Aug 19 04:38:41 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 194212 kb
Host smart-4832fe05-23db-43b5-b636-ab88704dcaab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135189281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2135189281
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1618357964
Short name T731
Test name
Test status
Simulation time 11745841 ps
CPU time 0.57 seconds
Started Aug 19 04:38:37 PM PDT 24
Finished Aug 19 04:38:38 PM PDT 24
Peak memory 194840 kb
Host smart-5029640a-364e-4485-9933-b07514284818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618357964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1618357964
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3921739989
Short name T742
Test name
Test status
Simulation time 12013692 ps
CPU time 0.62 seconds
Started Aug 19 04:38:37 PM PDT 24
Finished Aug 19 04:38:38 PM PDT 24
Peak memory 194344 kb
Host smart-24afa6fd-c227-4ddb-99c7-5910c927c2a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921739989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3921739989
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3360340027
Short name T764
Test name
Test status
Simulation time 14244335 ps
CPU time 0.55 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 194240 kb
Host smart-41ab8a98-4a8a-46e9-89ff-50a74002f2e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360340027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3360340027
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3604910367
Short name T78
Test name
Test status
Simulation time 35612775 ps
CPU time 0.86 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 196292 kb
Host smart-74164636-63cb-4e60-93c6-222a85575023
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604910367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3604910367
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.74686498
Short name T835
Test name
Test status
Simulation time 775924450 ps
CPU time 2.3 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:38:09 PM PDT 24
Peak memory 197372 kb
Host smart-a52377a8-ac8f-4195-a5bd-00a2fd1e8dc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74686498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.74686498
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2600352456
Short name T785
Test name
Test status
Simulation time 53802425 ps
CPU time 0.62 seconds
Started Aug 19 04:38:12 PM PDT 24
Finished Aug 19 04:38:13 PM PDT 24
Peak memory 195296 kb
Host smart-9f422f33-7af3-4f3e-8707-5c881a330441
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600352456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2600352456
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3993936881
Short name T795
Test name
Test status
Simulation time 43172068 ps
CPU time 1.08 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:28 PM PDT 24
Peak memory 198400 kb
Host smart-8676bcec-ac1a-4bdf-a81d-6d40fb415d4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993936881 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3993936881
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2141290409
Short name T810
Test name
Test status
Simulation time 50551642 ps
CPU time 0.58 seconds
Started Aug 19 04:38:24 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 194412 kb
Host smart-8dcd04da-fa85-49e1-b992-d85c5d997620
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141290409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2141290409
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1035760318
Short name T762
Test name
Test status
Simulation time 13715387 ps
CPU time 0.56 seconds
Started Aug 19 04:38:21 PM PDT 24
Finished Aug 19 04:38:22 PM PDT 24
Peak memory 194284 kb
Host smart-4f230aad-4b83-4ec6-9be8-dbb4391212f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035760318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1035760318
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2610583288
Short name T83
Test name
Test status
Simulation time 25333037 ps
CPU time 0.64 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 195256 kb
Host smart-9bbcb432-ef97-4187-bbb4-600759942021
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610583288 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2610583288
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2827970586
Short name T794
Test name
Test status
Simulation time 75574482 ps
CPU time 1.11 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:31 PM PDT 24
Peak memory 198616 kb
Host smart-7d29e76f-e499-4a7f-b249-0fb597154a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827970586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2827970586
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1526286715
Short name T834
Test name
Test status
Simulation time 241401868 ps
CPU time 1.35 seconds
Started Aug 19 04:38:21 PM PDT 24
Finished Aug 19 04:38:23 PM PDT 24
Peak memory 198536 kb
Host smart-0f1b9a5e-6224-45ad-8587-38bcb7509036
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526286715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1526286715
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.791292170
Short name T730
Test name
Test status
Simulation time 20637789 ps
CPU time 0.57 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 194204 kb
Host smart-69523727-39ed-439c-9570-4a23f01d11d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791292170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.791292170
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.575462089
Short name T768
Test name
Test status
Simulation time 61534274 ps
CPU time 0.58 seconds
Started Aug 19 04:38:41 PM PDT 24
Finished Aug 19 04:38:42 PM PDT 24
Peak memory 194232 kb
Host smart-3cf8a6bb-7391-4429-959e-39eb831f20eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575462089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.575462089
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.193408560
Short name T735
Test name
Test status
Simulation time 23411767 ps
CPU time 0.63 seconds
Started Aug 19 04:38:39 PM PDT 24
Finished Aug 19 04:38:40 PM PDT 24
Peak memory 194812 kb
Host smart-b6a19b3a-8bd7-4e04-9328-7f87d7a9321c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193408560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.193408560
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1166174229
Short name T718
Test name
Test status
Simulation time 46125685 ps
CPU time 0.57 seconds
Started Aug 19 04:38:42 PM PDT 24
Finished Aug 19 04:38:42 PM PDT 24
Peak memory 194152 kb
Host smart-f773f273-fb34-4222-bfdc-36b063c4ed78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166174229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1166174229
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1747381376
Short name T740
Test name
Test status
Simulation time 21848919 ps
CPU time 0.55 seconds
Started Aug 19 04:38:41 PM PDT 24
Finished Aug 19 04:38:42 PM PDT 24
Peak memory 194220 kb
Host smart-c73bc184-706f-4712-9723-21a2e9147939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747381376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1747381376
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2038032744
Short name T825
Test name
Test status
Simulation time 17603289 ps
CPU time 0.61 seconds
Started Aug 19 04:38:39 PM PDT 24
Finished Aug 19 04:38:40 PM PDT 24
Peak memory 194280 kb
Host smart-b0715013-78a0-47a1-aecc-2e788e40a620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038032744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2038032744
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.775135360
Short name T788
Test name
Test status
Simulation time 69899598 ps
CPU time 0.58 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:40 PM PDT 24
Peak memory 194264 kb
Host smart-b52698b0-99e2-4d21-af90-463a4c869c49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775135360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.775135360
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1271064215
Short name T838
Test name
Test status
Simulation time 13098607 ps
CPU time 0.58 seconds
Started Aug 19 04:38:40 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 194320 kb
Host smart-e9a10324-044e-400e-9bfa-cc9199f820d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271064215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1271064215
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.313396805
Short name T736
Test name
Test status
Simulation time 12744866 ps
CPU time 0.56 seconds
Started Aug 19 04:38:42 PM PDT 24
Finished Aug 19 04:38:42 PM PDT 24
Peak memory 194096 kb
Host smart-95dbe28b-ae4b-4e99-9d23-f7c3cb10a217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313396805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.313396805
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1993864008
Short name T774
Test name
Test status
Simulation time 44431785 ps
CPU time 0.6 seconds
Started Aug 19 04:38:38 PM PDT 24
Finished Aug 19 04:38:39 PM PDT 24
Peak memory 194264 kb
Host smart-05c1705e-3193-4caf-8fa8-c422203738df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993864008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1993864008
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2744614059
Short name T827
Test name
Test status
Simulation time 37717063 ps
CPU time 0.98 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 198404 kb
Host smart-a9277e73-7a37-44c2-b619-00e53309cde7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744614059 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2744614059
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.974008834
Short name T818
Test name
Test status
Simulation time 14646119 ps
CPU time 0.59 seconds
Started Aug 19 04:38:12 PM PDT 24
Finished Aug 19 04:38:13 PM PDT 24
Peak memory 194964 kb
Host smart-51ee1e17-16ef-4127-b41a-848539331371
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974008834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.974008834
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2520203634
Short name T725
Test name
Test status
Simulation time 12798658 ps
CPU time 0.58 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 194760 kb
Host smart-defc2a13-fe96-4815-9b6a-ea6092ff2c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520203634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2520203634
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3159402537
Short name T68
Test name
Test status
Simulation time 54026552 ps
CPU time 0.82 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 197448 kb
Host smart-ded9da2b-1aca-4cdb-a64b-a34fa155a354
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159402537 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3159402537
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3962751559
Short name T822
Test name
Test status
Simulation time 138308659 ps
CPU time 1.44 seconds
Started Aug 19 04:38:24 PM PDT 24
Finished Aug 19 04:38:26 PM PDT 24
Peak memory 198648 kb
Host smart-013e33e5-a8af-4a36-8773-ea4072d3534f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962751559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3962751559
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3940726762
Short name T833
Test name
Test status
Simulation time 133150463 ps
CPU time 0.82 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:38:20 PM PDT 24
Peak memory 197680 kb
Host smart-6c74b40d-4c54-4152-9ebb-f5990a420959
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940726762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3940726762
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1642184781
Short name T755
Test name
Test status
Simulation time 56659068 ps
CPU time 0.91 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 198412 kb
Host smart-65a7b3d2-8ffe-4308-96b9-91064e267f2f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642184781 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1642184781
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3602587118
Short name T745
Test name
Test status
Simulation time 33580316 ps
CPU time 0.61 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 196004 kb
Host smart-c5189038-d43c-4074-80c2-732e37271188
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602587118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3602587118
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1497721044
Short name T746
Test name
Test status
Simulation time 22184938 ps
CPU time 0.61 seconds
Started Aug 19 04:38:10 PM PDT 24
Finished Aug 19 04:38:10 PM PDT 24
Peak memory 194224 kb
Host smart-1bdea06c-6fb5-4bca-91b8-d275851fdb4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497721044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1497721044
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2096361230
Short name T779
Test name
Test status
Simulation time 27673820 ps
CPU time 0.64 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 195604 kb
Host smart-f72c995d-5e37-44a7-a4ce-6b4cf53e8a50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096361230 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2096361230
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4053524282
Short name T831
Test name
Test status
Simulation time 161723144 ps
CPU time 2.25 seconds
Started Aug 19 04:38:21 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 198616 kb
Host smart-3218504c-b763-4875-85f8-699d45029171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053524282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4053524282
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.716788053
Short name T45
Test name
Test status
Simulation time 1348494008 ps
CPU time 1.08 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 198560 kb
Host smart-fc7cf11a-526b-4488-b0f7-e01dff860af4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716788053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.716788053
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2974842938
Short name T800
Test name
Test status
Simulation time 27257808 ps
CPU time 1.15 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:28 PM PDT 24
Peak memory 198576 kb
Host smart-156c432d-d619-43b2-bf45-518c2baf207b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974842938 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2974842938
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3084105906
Short name T821
Test name
Test status
Simulation time 12459729 ps
CPU time 0.58 seconds
Started Aug 19 04:38:10 PM PDT 24
Finished Aug 19 04:38:10 PM PDT 24
Peak memory 194440 kb
Host smart-6f06612f-06b0-49ad-af45-fdfb918fdfaf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084105906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3084105906
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3416067208
Short name T781
Test name
Test status
Simulation time 27624991 ps
CPU time 0.59 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 194184 kb
Host smart-d9f5fcb8-711d-4624-bf8b-a21e27d7245c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416067208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3416067208
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2849934000
Short name T787
Test name
Test status
Simulation time 19575572 ps
CPU time 0.62 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 195288 kb
Host smart-4ca35f4f-24a8-4545-af6f-f4a69eadc2f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849934000 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2849934000
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.4020219607
Short name T816
Test name
Test status
Simulation time 92375307 ps
CPU time 2.05 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:31 PM PDT 24
Peak memory 198592 kb
Host smart-b47791fc-8e7c-4ad5-a3a9-2b05f521ab9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020219607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.4020219607
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2091467680
Short name T807
Test name
Test status
Simulation time 180978663 ps
CPU time 1.16 seconds
Started Aug 19 04:38:16 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 198060 kb
Host smart-f0250235-3666-48c7-a675-2574e472325a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091467680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2091467680
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.791809366
Short name T733
Test name
Test status
Simulation time 19200748 ps
CPU time 0.67 seconds
Started Aug 19 04:38:35 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 197840 kb
Host smart-0cf02166-1a64-4d5c-824b-d3b7b3089331
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791809366 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.791809366
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.831370235
Short name T88
Test name
Test status
Simulation time 18500447 ps
CPU time 0.62 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 195396 kb
Host smart-3dd3ffdd-5c5e-41d5-a977-14e869d039a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831370235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.831370235
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3339735344
Short name T732
Test name
Test status
Simulation time 47354112 ps
CPU time 0.6 seconds
Started Aug 19 04:38:29 PM PDT 24
Finished Aug 19 04:38:30 PM PDT 24
Peak memory 194352 kb
Host smart-b76cf696-6c9b-4ebc-9bd2-f5d2d15715d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339735344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3339735344
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2398740124
Short name T82
Test name
Test status
Simulation time 76168275 ps
CPU time 0.62 seconds
Started Aug 19 04:38:16 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 194808 kb
Host smart-349e806c-77d4-4dc0-8bea-2d65f74cfae2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398740124 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2398740124
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2249429456
Short name T771
Test name
Test status
Simulation time 24781831 ps
CPU time 1.16 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 198620 kb
Host smart-450de8f3-bec2-41cb-9f63-50761c128ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249429456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2249429456
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1862958238
Short name T46
Test name
Test status
Simulation time 514891817 ps
CPU time 1.15 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 198456 kb
Host smart-10c5c4d2-50c1-4695-98c7-53ec4a856f5e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862958238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1862958238
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1617116314
Short name T741
Test name
Test status
Simulation time 26536145 ps
CPU time 1.2 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 198588 kb
Host smart-361ec09c-e107-444f-9786-de4a6547ec42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617116314 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1617116314
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3357268998
Short name T824
Test name
Test status
Simulation time 44158205 ps
CPU time 0.59 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 195800 kb
Host smart-42f1d039-0173-422a-9084-e13be1999553
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357268998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3357268998
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.855297125
Short name T839
Test name
Test status
Simulation time 45978957 ps
CPU time 0.58 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 194224 kb
Host smart-a5fcae23-5349-4aa2-aad8-fa53e1e40176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855297125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.855297125
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1623442729
Short name T69
Test name
Test status
Simulation time 36390383 ps
CPU time 0.8 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 196452 kb
Host smart-b04ac27a-db20-40be-929a-b948e16417d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623442729 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1623442729
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1428159639
Short name T738
Test name
Test status
Simulation time 69715106 ps
CPU time 1.58 seconds
Started Aug 19 04:38:27 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 198600 kb
Host smart-79c59711-081b-41f4-8214-67c8d307ca62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428159639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1428159639
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1560469938
Short name T828
Test name
Test status
Simulation time 40705921 ps
CPU time 0.87 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 197364 kb
Host smart-a2954d1e-9aac-4a6e-86c7-2b388afbadb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560469938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1560469938
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3898573115
Short name T219
Test name
Test status
Simulation time 52551285 ps
CPU time 0.88 seconds
Started Aug 19 05:22:04 PM PDT 24
Finished Aug 19 05:22:05 PM PDT 24
Peak memory 196432 kb
Host smart-680d20c9-9839-4111-991a-85b712760748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898573115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3898573115
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.465261491
Short name T459
Test name
Test status
Simulation time 499741779 ps
CPU time 4.76 seconds
Started Aug 19 05:22:10 PM PDT 24
Finished Aug 19 05:22:15 PM PDT 24
Peak memory 195676 kb
Host smart-f0105a0f-378b-46f1-bb76-7cf8d069dd87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465261491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.465261491
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3898226613
Short name T410
Test name
Test status
Simulation time 144655072 ps
CPU time 0.66 seconds
Started Aug 19 05:22:05 PM PDT 24
Finished Aug 19 05:22:06 PM PDT 24
Peak memory 194708 kb
Host smart-aee91780-cd6a-4d3a-842d-ff488327c887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898226613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3898226613
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3669560021
Short name T392
Test name
Test status
Simulation time 165946612 ps
CPU time 1.2 seconds
Started Aug 19 05:22:10 PM PDT 24
Finished Aug 19 05:22:11 PM PDT 24
Peak memory 196352 kb
Host smart-25a565cb-c10f-4fbd-a9d5-1c3c7053d730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669560021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3669560021
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2822556787
Short name T332
Test name
Test status
Simulation time 399804545 ps
CPU time 2.28 seconds
Started Aug 19 05:22:04 PM PDT 24
Finished Aug 19 05:22:06 PM PDT 24
Peak memory 198208 kb
Host smart-dd16f3f2-47aa-48fc-ab63-d5ebbcf54766
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822556787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2822556787
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2354496795
Short name T664
Test name
Test status
Simulation time 181997296 ps
CPU time 1.52 seconds
Started Aug 19 05:22:05 PM PDT 24
Finished Aug 19 05:22:07 PM PDT 24
Peak memory 196356 kb
Host smart-b8899711-be2b-4848-a2b1-a2c32b8dcc88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354496795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2354496795
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3755701564
Short name T109
Test name
Test status
Simulation time 39672986 ps
CPU time 1.02 seconds
Started Aug 19 05:22:10 PM PDT 24
Finished Aug 19 05:22:11 PM PDT 24
Peak memory 195972 kb
Host smart-abbca859-5cc7-4422-8f85-2a51f7a761f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755701564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3755701564
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.543356694
Short name T615
Test name
Test status
Simulation time 236838479 ps
CPU time 1.01 seconds
Started Aug 19 05:22:04 PM PDT 24
Finished Aug 19 05:22:05 PM PDT 24
Peak memory 196804 kb
Host smart-a323fd3a-c1a9-4c25-aa86-10611ec7e03e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543356694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.543356694
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2448938226
Short name T596
Test name
Test status
Simulation time 136975374 ps
CPU time 2.26 seconds
Started Aug 19 05:22:05 PM PDT 24
Finished Aug 19 05:22:07 PM PDT 24
Peak memory 198160 kb
Host smart-8e7b0b51-d2d9-4a3c-8c1b-43e65e983ae0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448938226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2448938226
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2232769585
Short name T38
Test name
Test status
Simulation time 348867204 ps
CPU time 0.95 seconds
Started Aug 19 05:22:04 PM PDT 24
Finished Aug 19 05:22:05 PM PDT 24
Peak memory 215092 kb
Host smart-2dd21db2-50ca-4cf5-9a72-a54a86b01a62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232769585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2232769585
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1878962937
Short name T420
Test name
Test status
Simulation time 526811165 ps
CPU time 0.88 seconds
Started Aug 19 05:22:05 PM PDT 24
Finished Aug 19 05:22:06 PM PDT 24
Peak memory 195396 kb
Host smart-f388eb69-0629-4123-a95a-d83f9529091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878962937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1878962937
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.312264235
Short name T345
Test name
Test status
Simulation time 150800282 ps
CPU time 0.94 seconds
Started Aug 19 05:22:04 PM PDT 24
Finished Aug 19 05:22:05 PM PDT 24
Peak memory 197320 kb
Host smart-67db5c44-7b09-496c-b7c3-2bf7173cb943
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312264235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.312264235
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2038714064
Short name T320
Test name
Test status
Simulation time 19544937583 ps
CPU time 74.49 seconds
Started Aug 19 05:22:04 PM PDT 24
Finished Aug 19 05:23:18 PM PDT 24
Peak memory 198376 kb
Host smart-f11bb3c2-f55c-4bb3-8e7d-977857abed4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038714064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2038714064
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.123330737
Short name T65
Test name
Test status
Simulation time 5475142335 ps
CPU time 196.52 seconds
Started Aug 19 05:22:06 PM PDT 24
Finished Aug 19 05:25:22 PM PDT 24
Peak memory 198572 kb
Host smart-c2ef566d-aedc-447d-acd9-b1431f4f8cc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=123330737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.123330737
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.8770445
Short name T326
Test name
Test status
Simulation time 38209957 ps
CPU time 0.58 seconds
Started Aug 19 05:22:17 PM PDT 24
Finished Aug 19 05:22:18 PM PDT 24
Peak memory 194988 kb
Host smart-153b4da4-8f2e-4033-a6b0-f8a6cfdf8a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8770445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.8770445
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.510171725
Short name T289
Test name
Test status
Simulation time 40329676 ps
CPU time 0.68 seconds
Started Aug 19 05:22:18 PM PDT 24
Finished Aug 19 05:22:19 PM PDT 24
Peak memory 194884 kb
Host smart-3ad1dfa0-f3e6-4dbb-8aa2-a25df1c6d74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510171725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.510171725
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3296475354
Short name T579
Test name
Test status
Simulation time 129961770 ps
CPU time 4.82 seconds
Started Aug 19 05:22:16 PM PDT 24
Finished Aug 19 05:22:21 PM PDT 24
Peak memory 195936 kb
Host smart-f10966d9-6e66-4605-b081-f09848ded354
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296475354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3296475354
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1443111456
Short name T555
Test name
Test status
Simulation time 19135138 ps
CPU time 0.64 seconds
Started Aug 19 05:22:18 PM PDT 24
Finished Aug 19 05:22:19 PM PDT 24
Peak memory 195172 kb
Host smart-8cf302c4-7bcf-4396-82b3-a249fffc0c21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443111456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1443111456
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.263569579
Short name T387
Test name
Test status
Simulation time 178349005 ps
CPU time 0.92 seconds
Started Aug 19 05:22:19 PM PDT 24
Finished Aug 19 05:22:20 PM PDT 24
Peak memory 197332 kb
Host smart-85ebf01e-e99c-44ce-a033-4d9eff0fc503
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263569579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.263569579
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1877128758
Short name T185
Test name
Test status
Simulation time 61588318 ps
CPU time 2.68 seconds
Started Aug 19 05:22:16 PM PDT 24
Finished Aug 19 05:22:19 PM PDT 24
Peak memory 198248 kb
Host smart-c14addde-b033-4887-b17b-26641b04b754
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877128758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1877128758
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1857124529
Short name T113
Test name
Test status
Simulation time 130421174 ps
CPU time 2.08 seconds
Started Aug 19 05:22:18 PM PDT 24
Finished Aug 19 05:22:20 PM PDT 24
Peak memory 197240 kb
Host smart-ead9a252-0545-4930-9e11-8a59511d9cb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857124529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1857124529
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2190721749
Short name T561
Test name
Test status
Simulation time 21832757 ps
CPU time 0.89 seconds
Started Aug 19 05:22:06 PM PDT 24
Finished Aug 19 05:22:07 PM PDT 24
Peak memory 197392 kb
Host smart-2e3b079f-da92-43d1-ae5a-9c0aad7f1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190721749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2190721749
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3368631138
Short name T189
Test name
Test status
Simulation time 120518225 ps
CPU time 1.24 seconds
Started Aug 19 05:22:18 PM PDT 24
Finished Aug 19 05:22:20 PM PDT 24
Peak memory 196000 kb
Host smart-216d1e5b-1bfc-43a9-a1cc-e71af5d3cbce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368631138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3368631138
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.280069673
Short name T542
Test name
Test status
Simulation time 310655072 ps
CPU time 2.18 seconds
Started Aug 19 05:22:18 PM PDT 24
Finished Aug 19 05:22:20 PM PDT 24
Peak memory 198160 kb
Host smart-d061fe1c-a14f-45b5-b2d8-66040478d06f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280069673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.280069673
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3514473355
Short name T48
Test name
Test status
Simulation time 152870899 ps
CPU time 0.96 seconds
Started Aug 19 05:22:17 PM PDT 24
Finished Aug 19 05:22:18 PM PDT 24
Peak memory 215180 kb
Host smart-0be5a9d0-4410-4520-b3bf-1a1cd8f48229
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514473355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3514473355
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.850836485
Short name T385
Test name
Test status
Simulation time 57390865 ps
CPU time 1.3 seconds
Started Aug 19 05:22:03 PM PDT 24
Finished Aug 19 05:22:05 PM PDT 24
Peak memory 196492 kb
Host smart-ffa016f8-649d-4593-a789-1aadcbc00be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850836485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.850836485
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.72281345
Short name T297
Test name
Test status
Simulation time 34184830 ps
CPU time 1.16 seconds
Started Aug 19 05:22:05 PM PDT 24
Finished Aug 19 05:22:06 PM PDT 24
Peak memory 196592 kb
Host smart-aeeaa12d-924a-49b2-8bf4-c27604afaf1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72281345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.72281345
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.692273409
Short name T226
Test name
Test status
Simulation time 22794983280 ps
CPU time 77.4 seconds
Started Aug 19 05:22:16 PM PDT 24
Finished Aug 19 05:23:34 PM PDT 24
Peak memory 198372 kb
Host smart-41d0d5ec-10de-46e3-a352-9ef0a56da75c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692273409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.692273409
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1240974536
Short name T690
Test name
Test status
Simulation time 43053749 ps
CPU time 0.59 seconds
Started Aug 19 05:23:11 PM PDT 24
Finished Aug 19 05:23:11 PM PDT 24
Peak memory 194220 kb
Host smart-5a1d66e4-6740-42a3-8900-36dced2ac818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240974536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1240974536
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2270432274
Short name T148
Test name
Test status
Simulation time 16486317 ps
CPU time 0.71 seconds
Started Aug 19 05:23:03 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 194012 kb
Host smart-c2f55b6e-de6a-47c1-ae9b-38ecf4b48530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270432274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2270432274
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1431121813
Short name T250
Test name
Test status
Simulation time 183801234 ps
CPU time 6.49 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:09 PM PDT 24
Peak memory 196448 kb
Host smart-35dfa7a9-0d2b-490e-9733-e2094eac0331
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431121813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1431121813
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3024689362
Short name T566
Test name
Test status
Simulation time 105587121 ps
CPU time 0.71 seconds
Started Aug 19 05:23:12 PM PDT 24
Finished Aug 19 05:23:13 PM PDT 24
Peak memory 194748 kb
Host smart-1d30f465-c666-4069-91b9-6b6383f70e59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024689362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3024689362
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.993887214
Short name T427
Test name
Test status
Simulation time 124425271 ps
CPU time 0.92 seconds
Started Aug 19 05:23:04 PM PDT 24
Finished Aug 19 05:23:05 PM PDT 24
Peak memory 196976 kb
Host smart-88611f3b-e2f1-4cd8-9f34-6eb601e4aa13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993887214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.993887214
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3300184407
Short name T54
Test name
Test status
Simulation time 66163759 ps
CPU time 2.75 seconds
Started Aug 19 05:23:04 PM PDT 24
Finished Aug 19 05:23:07 PM PDT 24
Peak memory 198216 kb
Host smart-3d8a8dec-4096-44cc-b6fc-96aa5dd48d80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300184407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3300184407
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3713115580
Short name T193
Test name
Test status
Simulation time 210251881 ps
CPU time 1.15 seconds
Started Aug 19 05:23:01 PM PDT 24
Finished Aug 19 05:23:02 PM PDT 24
Peak memory 195620 kb
Host smart-fcd2d2d4-6e31-4b9e-b9e3-19b552601b15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713115580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3713115580
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2738315114
Short name T225
Test name
Test status
Simulation time 27072927 ps
CPU time 0.73 seconds
Started Aug 19 05:23:04 PM PDT 24
Finished Aug 19 05:23:05 PM PDT 24
Peak memory 195544 kb
Host smart-24cd2428-bc5c-4ea5-a1cf-a35fc06401ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738315114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2738315114
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2386747995
Short name T121
Test name
Test status
Simulation time 76904709 ps
CPU time 0.76 seconds
Started Aug 19 05:23:04 PM PDT 24
Finished Aug 19 05:23:05 PM PDT 24
Peak memory 195476 kb
Host smart-dae96a61-991c-4b55-8b6f-a24859997d81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386747995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2386747995
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2660574330
Short name T361
Test name
Test status
Simulation time 521167834 ps
CPU time 5.91 seconds
Started Aug 19 05:23:16 PM PDT 24
Finished Aug 19 05:23:22 PM PDT 24
Peak memory 198164 kb
Host smart-5a08ac50-111c-46de-b8ad-54d3e0984b98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660574330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2660574330
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2386346025
Short name T599
Test name
Test status
Simulation time 124838473 ps
CPU time 1.14 seconds
Started Aug 19 05:23:04 PM PDT 24
Finished Aug 19 05:23:05 PM PDT 24
Peak memory 195852 kb
Host smart-950e66f1-4329-4227-a964-140cea81da68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386346025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2386346025
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2045665110
Short name T636
Test name
Test status
Simulation time 420918074 ps
CPU time 1.28 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 196692 kb
Host smart-28a4bf3a-a76e-4ac6-b4b7-d677ab14bdee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045665110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2045665110
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3704977155
Short name T609
Test name
Test status
Simulation time 7313496282 ps
CPU time 104.15 seconds
Started Aug 19 05:23:11 PM PDT 24
Finished Aug 19 05:24:55 PM PDT 24
Peak memory 198356 kb
Host smart-ab55b177-a386-4a6b-98b7-bd2e2402ac01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704977155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3704977155
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.54427635
Short name T243
Test name
Test status
Simulation time 9542558364 ps
CPU time 68.91 seconds
Started Aug 19 05:23:11 PM PDT 24
Finished Aug 19 05:24:20 PM PDT 24
Peak memory 198564 kb
Host smart-51d73c9c-ab60-4a8e-a644-6fff154c1d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=54427635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.54427635
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.161428573
Short name T489
Test name
Test status
Simulation time 28918149 ps
CPU time 0.54 seconds
Started Aug 19 05:23:09 PM PDT 24
Finished Aug 19 05:23:10 PM PDT 24
Peak memory 194024 kb
Host smart-581cade8-2fb8-43b5-9416-02f8e004a570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161428573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.161428573
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1478926666
Short name T454
Test name
Test status
Simulation time 21573892 ps
CPU time 0.64 seconds
Started Aug 19 05:23:12 PM PDT 24
Finished Aug 19 05:23:13 PM PDT 24
Peak memory 194120 kb
Host smart-6417e17b-e29b-44c2-b935-3ffa9055a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478926666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1478926666
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1182593100
Short name T552
Test name
Test status
Simulation time 2927160770 ps
CPU time 19.51 seconds
Started Aug 19 05:23:09 PM PDT 24
Finished Aug 19 05:23:29 PM PDT 24
Peak memory 197248 kb
Host smart-93687e87-78ae-4e6a-872b-2be34af556ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182593100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1182593100
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3823805047
Short name T240
Test name
Test status
Simulation time 164823789 ps
CPU time 0.78 seconds
Started Aug 19 05:23:16 PM PDT 24
Finished Aug 19 05:23:17 PM PDT 24
Peak memory 196828 kb
Host smart-7379ca0e-358a-43f2-b11d-694a36ec36e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823805047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3823805047
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.609824078
Short name T571
Test name
Test status
Simulation time 124718982 ps
CPU time 1.03 seconds
Started Aug 19 05:23:13 PM PDT 24
Finished Aug 19 05:23:14 PM PDT 24
Peak memory 196236 kb
Host smart-6ad42e48-34bf-41d0-9d19-5a4a60115759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609824078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.609824078
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1405901367
Short name T192
Test name
Test status
Simulation time 250957070 ps
CPU time 2.92 seconds
Started Aug 19 05:23:12 PM PDT 24
Finished Aug 19 05:23:15 PM PDT 24
Peak memory 197196 kb
Host smart-052e4d99-4348-4e27-953d-2e7b7e1b4c31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405901367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1405901367
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1314795064
Short name T154
Test name
Test status
Simulation time 74616771 ps
CPU time 0.94 seconds
Started Aug 19 05:23:10 PM PDT 24
Finished Aug 19 05:23:12 PM PDT 24
Peak memory 196676 kb
Host smart-1ddc15dd-0ec6-4e57-9a91-d99379906529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314795064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1314795064
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2516519744
Short name T259
Test name
Test status
Simulation time 201138669 ps
CPU time 1.03 seconds
Started Aug 19 05:23:11 PM PDT 24
Finished Aug 19 05:23:12 PM PDT 24
Peak memory 196152 kb
Host smart-f988b27d-4962-462b-8725-30ec56ecd1f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516519744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2516519744
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.4092236311
Short name T484
Test name
Test status
Simulation time 161713524 ps
CPU time 1.65 seconds
Started Aug 19 05:23:11 PM PDT 24
Finished Aug 19 05:23:13 PM PDT 24
Peak memory 198004 kb
Host smart-dbace443-3b8d-4d1c-ad0c-d37175776abc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092236311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.4092236311
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1519535824
Short name T173
Test name
Test status
Simulation time 151070053 ps
CPU time 0.98 seconds
Started Aug 19 05:23:12 PM PDT 24
Finished Aug 19 05:23:13 PM PDT 24
Peak memory 196728 kb
Host smart-6ca27261-d566-4d44-869c-d45695d171b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519535824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1519535824
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3310884841
Short name T412
Test name
Test status
Simulation time 89931616 ps
CPU time 1 seconds
Started Aug 19 05:23:14 PM PDT 24
Finished Aug 19 05:23:15 PM PDT 24
Peak memory 195592 kb
Host smart-8a27c5a7-e847-48fd-816b-78ccc2cc04ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310884841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3310884841
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1156227978
Short name T707
Test name
Test status
Simulation time 7972478109 ps
CPU time 77.18 seconds
Started Aug 19 05:23:12 PM PDT 24
Finished Aug 19 05:24:29 PM PDT 24
Peak memory 198396 kb
Host smart-e4d7a994-a71b-420a-940c-12ce116ec69d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156227978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1156227978
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.218060968
Short name T64
Test name
Test status
Simulation time 1648898242 ps
CPU time 24.37 seconds
Started Aug 19 05:23:15 PM PDT 24
Finished Aug 19 05:23:39 PM PDT 24
Peak memory 198400 kb
Host smart-616403c3-3ef6-4b4c-a031-1231d7a8812b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=218060968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.218060968
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3526379710
Short name T237
Test name
Test status
Simulation time 38002639 ps
CPU time 0.57 seconds
Started Aug 19 05:23:19 PM PDT 24
Finished Aug 19 05:23:19 PM PDT 24
Peak memory 194044 kb
Host smart-d841e3b3-a038-4626-9c2c-2aa39bc8dd99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526379710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3526379710
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1198102454
Short name T551
Test name
Test status
Simulation time 89971579 ps
CPU time 0.71 seconds
Started Aug 19 05:23:22 PM PDT 24
Finished Aug 19 05:23:22 PM PDT 24
Peak memory 196020 kb
Host smart-2dc9757e-ee41-440a-88d0-ad25c458b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198102454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1198102454
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1968906319
Short name T458
Test name
Test status
Simulation time 224636775 ps
CPU time 10.98 seconds
Started Aug 19 05:23:19 PM PDT 24
Finished Aug 19 05:23:30 PM PDT 24
Peak memory 196928 kb
Host smart-d55c8836-7767-4ada-a399-f1a2da47ed0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968906319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1968906319
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4189558520
Short name T642
Test name
Test status
Simulation time 87245062 ps
CPU time 0.77 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:23:21 PM PDT 24
Peak memory 195912 kb
Host smart-53d342de-8d2a-49ab-8ec8-6a4931f5b0fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189558520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4189558520
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.715018566
Short name T576
Test name
Test status
Simulation time 85126279 ps
CPU time 0.73 seconds
Started Aug 19 05:23:19 PM PDT 24
Finished Aug 19 05:23:20 PM PDT 24
Peak memory 195280 kb
Host smart-c261d253-cba8-4fc2-b1db-3eb31b56450d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715018566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.715018566
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3761803788
Short name T643
Test name
Test status
Simulation time 345634811 ps
CPU time 3.56 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:23:24 PM PDT 24
Peak memory 198228 kb
Host smart-057a0474-969f-4149-b23a-a1fff78e0d27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761803788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3761803788
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.318056512
Short name T476
Test name
Test status
Simulation time 65806186 ps
CPU time 2.19 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:23:22 PM PDT 24
Peak memory 196024 kb
Host smart-e9c7387b-e3ae-4705-90ff-e57924c186d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318056512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
318056512
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1278146420
Short name T15
Test name
Test status
Simulation time 111165801 ps
CPU time 1.17 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:23:21 PM PDT 24
Peak memory 195972 kb
Host smart-8302ffc5-585d-4700-9b44-9672cb9954de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278146420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1278146420
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1535733087
Short name T223
Test name
Test status
Simulation time 21812120 ps
CPU time 0.68 seconds
Started Aug 19 05:23:19 PM PDT 24
Finished Aug 19 05:23:20 PM PDT 24
Peak memory 194516 kb
Host smart-820dce42-d1a4-41b8-aa53-6531a89b4fc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535733087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1535733087
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1832592148
Short name T342
Test name
Test status
Simulation time 1298236811 ps
CPU time 4.99 seconds
Started Aug 19 05:23:18 PM PDT 24
Finished Aug 19 05:23:23 PM PDT 24
Peak memory 198176 kb
Host smart-86b93bad-bf60-4bf2-9ca1-5c11dd185ab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832592148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1832592148
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1302937514
Short name T693
Test name
Test status
Simulation time 31529369 ps
CPU time 0.83 seconds
Started Aug 19 05:23:11 PM PDT 24
Finished Aug 19 05:23:12 PM PDT 24
Peak memory 196200 kb
Host smart-53c94283-5a6d-44d1-beb7-eaf90429dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302937514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1302937514
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1667035992
Short name T216
Test name
Test status
Simulation time 214337049 ps
CPU time 1.23 seconds
Started Aug 19 05:23:16 PM PDT 24
Finished Aug 19 05:23:17 PM PDT 24
Peak memory 195912 kb
Host smart-ed955251-1a60-4491-8ce7-0cb649895ac6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667035992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1667035992
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2932255670
Short name T547
Test name
Test status
Simulation time 23746927949 ps
CPU time 87.97 seconds
Started Aug 19 05:23:22 PM PDT 24
Finished Aug 19 05:24:50 PM PDT 24
Peak memory 198392 kb
Host smart-aaa299cf-7775-43c0-a1c4-7724b5b2ab87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932255670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2932255670
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.4154717858
Short name T227
Test name
Test status
Simulation time 21890361598 ps
CPU time 199.97 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:26:40 PM PDT 24
Peak memory 198568 kb
Host smart-5f7f53c9-4c02-431c-bd67-53c2b49d2490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4154717858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.4154717858
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3752584668
Short name T122
Test name
Test status
Simulation time 38289398 ps
CPU time 0.56 seconds
Started Aug 19 05:23:33 PM PDT 24
Finished Aug 19 05:23:34 PM PDT 24
Peak memory 194084 kb
Host smart-76a952d8-8f86-40de-ae4d-a2cdc2e64ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752584668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3752584668
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1240355465
Short name T569
Test name
Test status
Simulation time 19716980 ps
CPU time 0.75 seconds
Started Aug 19 05:23:18 PM PDT 24
Finished Aug 19 05:23:19 PM PDT 24
Peak memory 195400 kb
Host smart-546a3f12-b3a5-4618-9f35-e1c00a4fa29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240355465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1240355465
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3533562066
Short name T646
Test name
Test status
Simulation time 1215613684 ps
CPU time 20.35 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:49 PM PDT 24
Peak memory 197016 kb
Host smart-b958ba36-898c-4817-b04c-6d9331e7e585
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533562066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3533562066
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.811629730
Short name T406
Test name
Test status
Simulation time 397396077 ps
CPU time 1.17 seconds
Started Aug 19 05:23:37 PM PDT 24
Finished Aug 19 05:23:38 PM PDT 24
Peak memory 196640 kb
Host smart-f63104ef-792f-457d-9724-f4684bab1498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811629730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.811629730
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1598714630
Short name T183
Test name
Test status
Simulation time 73500811 ps
CPU time 0.86 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:23:21 PM PDT 24
Peak memory 196880 kb
Host smart-f5574bbf-2107-458d-85b2-5251241db8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598714630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1598714630
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.63844615
Short name T171
Test name
Test status
Simulation time 95457544 ps
CPU time 1.53 seconds
Started Aug 19 05:23:34 PM PDT 24
Finished Aug 19 05:23:36 PM PDT 24
Peak memory 198052 kb
Host smart-93602a3e-bfd3-4cef-abbd-b0f2ad088251
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63844615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.gpio_intr_with_filter_rand_intr_event.63844615
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.4145410993
Short name T654
Test name
Test status
Simulation time 249245679 ps
CPU time 1.94 seconds
Started Aug 19 05:23:37 PM PDT 24
Finished Aug 19 05:23:39 PM PDT 24
Peak memory 197504 kb
Host smart-dd308e24-7ab0-479b-aa7c-89fa06fd21d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145410993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.4145410993
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3681670279
Short name T695
Test name
Test status
Simulation time 40498954 ps
CPU time 0.75 seconds
Started Aug 19 05:23:18 PM PDT 24
Finished Aug 19 05:23:19 PM PDT 24
Peak memory 195532 kb
Host smart-f9dc9826-8da1-4152-b2e3-54e5acb35986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681670279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3681670279
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2813601968
Short name T382
Test name
Test status
Simulation time 23515470 ps
CPU time 0.99 seconds
Started Aug 19 05:23:19 PM PDT 24
Finished Aug 19 05:23:20 PM PDT 24
Peak memory 196960 kb
Host smart-e742614d-40c9-4906-b445-96328f4aa3a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813601968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2813601968
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4247579131
Short name T694
Test name
Test status
Simulation time 476186325 ps
CPU time 2.24 seconds
Started Aug 19 05:23:31 PM PDT 24
Finished Aug 19 05:23:33 PM PDT 24
Peak memory 198176 kb
Host smart-e9fbd3bc-b653-4488-95d3-a344d17293d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247579131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4247579131
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.17642129
Short name T310
Test name
Test status
Simulation time 183203877 ps
CPU time 1.35 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:23:21 PM PDT 24
Peak memory 196872 kb
Host smart-bc64e704-49d2-4cbc-94d6-b162b024b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17642129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.17642129
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1131035572
Short name T661
Test name
Test status
Simulation time 65279191 ps
CPU time 0.96 seconds
Started Aug 19 05:23:20 PM PDT 24
Finished Aug 19 05:23:21 PM PDT 24
Peak memory 197352 kb
Host smart-45409330-e2ae-4f57-a667-cf934e5d74ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131035572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1131035572
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3772504280
Short name T600
Test name
Test status
Simulation time 6670449333 ps
CPU time 47.26 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:24:16 PM PDT 24
Peak memory 198364 kb
Host smart-ebf3590b-d3b1-4c5d-a82c-d02f8be6b77d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772504280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3772504280
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3196435345
Short name T253
Test name
Test status
Simulation time 3943905689 ps
CPU time 100.68 seconds
Started Aug 19 05:23:34 PM PDT 24
Finished Aug 19 05:25:15 PM PDT 24
Peak memory 198452 kb
Host smart-faf0fac9-9f7b-4827-9b67-b2e3ad443627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3196435345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3196435345
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1072353452
Short name T210
Test name
Test status
Simulation time 78185997 ps
CPU time 0.57 seconds
Started Aug 19 05:23:31 PM PDT 24
Finished Aug 19 05:23:31 PM PDT 24
Peak memory 194028 kb
Host smart-58d1a3cf-2035-4e89-89ad-d206df62eec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072353452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1072353452
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1614066550
Short name T505
Test name
Test status
Simulation time 102522578 ps
CPU time 0.97 seconds
Started Aug 19 05:23:32 PM PDT 24
Finished Aug 19 05:23:33 PM PDT 24
Peak memory 196716 kb
Host smart-311ca05e-c7db-45e8-a2e4-21494ae991a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614066550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1614066550
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3929688767
Short name T304
Test name
Test status
Simulation time 498598059 ps
CPU time 6.34 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:36 PM PDT 24
Peak memory 197140 kb
Host smart-d638956e-e226-486d-b48d-9c3049e766b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929688767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3929688767
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2577114926
Short name T8
Test name
Test status
Simulation time 154204114 ps
CPU time 0.88 seconds
Started Aug 19 05:23:34 PM PDT 24
Finished Aug 19 05:23:35 PM PDT 24
Peak memory 196232 kb
Host smart-c9114aeb-3f74-46d5-833b-97437dfa91eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577114926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2577114926
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4037678111
Short name T152
Test name
Test status
Simulation time 32970416 ps
CPU time 1.07 seconds
Started Aug 19 05:23:30 PM PDT 24
Finished Aug 19 05:23:31 PM PDT 24
Peak memory 196988 kb
Host smart-8d267c05-3907-4b47-8856-94bcedf41081
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037678111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4037678111
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1348470743
Short name T529
Test name
Test status
Simulation time 27552854 ps
CPU time 1.25 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:30 PM PDT 24
Peak memory 198116 kb
Host smart-5128a77c-6365-428d-a7ad-e34db0eeee3b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348470743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1348470743
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2010109126
Short name T168
Test name
Test status
Simulation time 227937940 ps
CPU time 1.6 seconds
Started Aug 19 05:23:31 PM PDT 24
Finished Aug 19 05:23:33 PM PDT 24
Peak memory 195988 kb
Host smart-fade3bfa-7100-42d9-8f74-bb8851671879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010109126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2010109126
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2949094258
Short name T634
Test name
Test status
Simulation time 234200983 ps
CPU time 1.46 seconds
Started Aug 19 05:23:30 PM PDT 24
Finished Aug 19 05:23:32 PM PDT 24
Peak memory 198220 kb
Host smart-27445a10-1623-46a3-9041-a70f0f0aa8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949094258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2949094258
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1022149394
Short name T315
Test name
Test status
Simulation time 215263238 ps
CPU time 1.36 seconds
Started Aug 19 05:23:31 PM PDT 24
Finished Aug 19 05:23:32 PM PDT 24
Peak memory 197188 kb
Host smart-41dc32d8-f6c0-447d-b6a6-0e3681fd493e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022149394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1022149394
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1885086013
Short name T367
Test name
Test status
Simulation time 616190977 ps
CPU time 1.93 seconds
Started Aug 19 05:23:30 PM PDT 24
Finished Aug 19 05:23:32 PM PDT 24
Peak memory 198116 kb
Host smart-09cf68c7-999e-4718-90ca-a76f9873fbf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885086013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1885086013
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1694690170
Short name T146
Test name
Test status
Simulation time 49739260 ps
CPU time 1.32 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:30 PM PDT 24
Peak memory 197044 kb
Host smart-113d9cad-22cb-43e0-a406-099a2c00f6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694690170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1694690170
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1910458787
Short name T426
Test name
Test status
Simulation time 339295879 ps
CPU time 1.25 seconds
Started Aug 19 05:23:31 PM PDT 24
Finished Aug 19 05:23:32 PM PDT 24
Peak memory 195996 kb
Host smart-203470d6-683d-446d-8b60-dacc62473746
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910458787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1910458787
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.373774464
Short name T482
Test name
Test status
Simulation time 4037220972 ps
CPU time 62.76 seconds
Started Aug 19 05:23:37 PM PDT 24
Finished Aug 19 05:24:40 PM PDT 24
Peak memory 198384 kb
Host smart-1446c3ac-c29c-46ad-949a-1ce2186c6c0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373774464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.373774464
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1976026863
Short name T61
Test name
Test status
Simulation time 4473422745 ps
CPU time 155.53 seconds
Started Aug 19 05:23:34 PM PDT 24
Finished Aug 19 05:26:10 PM PDT 24
Peak memory 198552 kb
Host smart-3c43df00-d9c3-414a-aaa2-5c41ada1d8bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1976026863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1976026863
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2677060514
Short name T194
Test name
Test status
Simulation time 12747568 ps
CPU time 0.62 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:30 PM PDT 24
Peak memory 194068 kb
Host smart-122d4711-b069-4c20-a3f4-f7d0c686046f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677060514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2677060514
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.117147450
Short name T102
Test name
Test status
Simulation time 99066816 ps
CPU time 0.95 seconds
Started Aug 19 05:23:34 PM PDT 24
Finished Aug 19 05:23:36 PM PDT 24
Peak memory 196832 kb
Host smart-950f817d-b99e-41f4-b526-a27f4f4b1a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117147450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.117147450
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1965868406
Short name T411
Test name
Test status
Simulation time 1989091704 ps
CPU time 29.61 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:59 PM PDT 24
Peak memory 196776 kb
Host smart-6fb6658a-b689-4c53-b4b1-d7611a3937c1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965868406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1965868406
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2330824558
Short name T548
Test name
Test status
Simulation time 117355440 ps
CPU time 0.8 seconds
Started Aug 19 05:23:30 PM PDT 24
Finished Aug 19 05:23:31 PM PDT 24
Peak memory 196008 kb
Host smart-7484e311-1d05-4bc4-9c3d-4f0603650d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330824558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2330824558
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1686625014
Short name T590
Test name
Test status
Simulation time 44192124 ps
CPU time 1.14 seconds
Started Aug 19 05:23:35 PM PDT 24
Finished Aug 19 05:23:37 PM PDT 24
Peak memory 196108 kb
Host smart-c0d2459f-1c72-4dca-b489-24e23c3b3182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686625014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1686625014
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.442629518
Short name T568
Test name
Test status
Simulation time 35723164 ps
CPU time 1.62 seconds
Started Aug 19 05:23:31 PM PDT 24
Finished Aug 19 05:23:33 PM PDT 24
Peak memory 196472 kb
Host smart-1f2ac4d3-0abf-49a0-b610-e045588964ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442629518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.442629518
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1121964768
Short name T425
Test name
Test status
Simulation time 437445645 ps
CPU time 3.27 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:32 PM PDT 24
Peak memory 198232 kb
Host smart-9bd3dc10-4dab-45ba-9271-16fc012458f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121964768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1121964768
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.659632663
Short name T184
Test name
Test status
Simulation time 31571186 ps
CPU time 1.35 seconds
Started Aug 19 05:23:31 PM PDT 24
Finished Aug 19 05:23:32 PM PDT 24
Peak memory 197312 kb
Host smart-0c36a144-a699-486d-91b3-9ae4ef467152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659632663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.659632663
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3905548582
Short name T492
Test name
Test status
Simulation time 107695129 ps
CPU time 1.15 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:31 PM PDT 24
Peak memory 195988 kb
Host smart-f17a4600-0f1b-4ba7-94c6-c07ddadda757
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905548582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3905548582
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.4161008920
Short name T404
Test name
Test status
Simulation time 332291925 ps
CPU time 3.7 seconds
Started Aug 19 05:23:30 PM PDT 24
Finished Aug 19 05:23:34 PM PDT 24
Peak memory 198084 kb
Host smart-b0d7def8-4782-4161-abc4-e5ac6b2bdac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161008920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.4161008920
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3495769050
Short name T358
Test name
Test status
Simulation time 49338821 ps
CPU time 1.08 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:30 PM PDT 24
Peak memory 196596 kb
Host smart-4e8f3a26-7388-43ca-ace4-846d33690679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495769050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3495769050
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.879729473
Short name T630
Test name
Test status
Simulation time 115167621 ps
CPU time 1.15 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 196900 kb
Host smart-39c9995d-d411-413b-bc3f-14e323d5ae14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879729473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.879729473
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3306273011
Short name T446
Test name
Test status
Simulation time 17968384769 ps
CPU time 119.58 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 192004 kb
Host smart-09786359-2cd6-4222-a8ea-e620380993b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306273011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3306273011
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.603925538
Short name T507
Test name
Test status
Simulation time 23058130 ps
CPU time 0.58 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:42 PM PDT 24
Peak memory 194256 kb
Host smart-cf4adc61-f256-4f1e-b71c-f3e7e5002bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603925538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.603925538
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.431492255
Short name T419
Test name
Test status
Simulation time 14726839 ps
CPU time 0.66 seconds
Started Aug 19 05:23:37 PM PDT 24
Finished Aug 19 05:23:38 PM PDT 24
Peak memory 194172 kb
Host smart-d74e4f2e-e6d5-4b6a-9a2a-2c85e5960d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431492255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.431492255
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1862858573
Short name T641
Test name
Test status
Simulation time 1538212881 ps
CPU time 21.38 seconds
Started Aug 19 05:23:41 PM PDT 24
Finished Aug 19 05:24:02 PM PDT 24
Peak memory 196888 kb
Host smart-8248e632-bac9-4092-ba02-b00b3dd9f82c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862858573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1862858573
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2893695236
Short name T314
Test name
Test status
Simulation time 39883685 ps
CPU time 0.78 seconds
Started Aug 19 05:23:41 PM PDT 24
Finished Aug 19 05:23:42 PM PDT 24
Peak memory 196008 kb
Host smart-ea4d6a97-617f-4ecb-9032-8775deb96347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893695236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2893695236
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2801241163
Short name T351
Test name
Test status
Simulation time 480538462 ps
CPU time 1.39 seconds
Started Aug 19 05:23:41 PM PDT 24
Finished Aug 19 05:23:42 PM PDT 24
Peak memory 196020 kb
Host smart-c9c33280-d9ab-497f-9360-57c1895feb5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801241163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2801241163
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3386699348
Short name T370
Test name
Test status
Simulation time 101298335 ps
CPU time 2.26 seconds
Started Aug 19 05:23:44 PM PDT 24
Finished Aug 19 05:23:46 PM PDT 24
Peak memory 198260 kb
Host smart-a499dca5-e84f-453a-a0eb-98ed8c8d3e1e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386699348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3386699348
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2845631177
Short name T657
Test name
Test status
Simulation time 112130097 ps
CPU time 3.06 seconds
Started Aug 19 05:23:39 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 197276 kb
Host smart-0734ef68-9ac0-434c-98ad-bccc09ab0cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845631177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2845631177
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3220322906
Short name T434
Test name
Test status
Simulation time 53854239 ps
CPU time 0.73 seconds
Started Aug 19 05:23:35 PM PDT 24
Finished Aug 19 05:23:36 PM PDT 24
Peak memory 195472 kb
Host smart-e166c20a-7518-4c31-9764-081dacbdb830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220322906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3220322906
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.4225344483
Short name T101
Test name
Test status
Simulation time 115010898 ps
CPU time 1.01 seconds
Started Aug 19 05:23:37 PM PDT 24
Finished Aug 19 05:23:38 PM PDT 24
Peak memory 196164 kb
Host smart-9818e988-8e9a-425a-930e-197ab29a4440
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225344483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.4225344483
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3237992555
Short name T162
Test name
Test status
Simulation time 240934660 ps
CPU time 1.34 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 198176 kb
Host smart-3483e25e-a821-4390-92b0-dd1954efe7f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237992555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3237992555
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2032993058
Short name T534
Test name
Test status
Simulation time 360753243 ps
CPU time 1.45 seconds
Started Aug 19 05:23:29 PM PDT 24
Finished Aug 19 05:23:31 PM PDT 24
Peak memory 198192 kb
Host smart-587d97cc-17b5-4c72-8f30-c2ee9c9fef2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032993058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2032993058
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3307318206
Short name T177
Test name
Test status
Simulation time 85038929 ps
CPU time 0.87 seconds
Started Aug 19 05:23:32 PM PDT 24
Finished Aug 19 05:23:34 PM PDT 24
Peak memory 196080 kb
Host smart-8276c5a6-49a1-4d45-820c-7235a747e3d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307318206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3307318206
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1682397194
Short name T99
Test name
Test status
Simulation time 5462019700 ps
CPU time 151.07 seconds
Started Aug 19 05:23:41 PM PDT 24
Finished Aug 19 05:26:13 PM PDT 24
Peak memory 198372 kb
Host smart-c05e2e84-d62d-46b3-a68a-1767f993b82c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682397194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1682397194
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.980062197
Short name T638
Test name
Test status
Simulation time 13553302 ps
CPU time 0.59 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 194108 kb
Host smart-80b810bc-29b9-40f1-8034-5120331622a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980062197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.980062197
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3438709479
Short name T340
Test name
Test status
Simulation time 278920263 ps
CPU time 0.92 seconds
Started Aug 19 05:23:44 PM PDT 24
Finished Aug 19 05:23:45 PM PDT 24
Peak memory 197348 kb
Host smart-526b6759-f518-4c97-9419-75d9781f7dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438709479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3438709479
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1378065317
Short name T432
Test name
Test status
Simulation time 3540339605 ps
CPU time 28.66 seconds
Started Aug 19 05:23:40 PM PDT 24
Finished Aug 19 05:24:09 PM PDT 24
Peak memory 197132 kb
Host smart-3eae84c1-617b-4dee-b096-ec4e7b0dc861
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378065317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1378065317
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2312983753
Short name T149
Test name
Test status
Simulation time 31786090 ps
CPU time 0.71 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 195640 kb
Host smart-9efd0750-963b-4ffa-89f0-43d9a9692eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312983753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2312983753
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2570099449
Short name T18
Test name
Test status
Simulation time 59072905 ps
CPU time 1.09 seconds
Started Aug 19 05:23:40 PM PDT 24
Finished Aug 19 05:23:42 PM PDT 24
Peak memory 196256 kb
Host smart-2d52c298-ca06-4ebe-b68a-9e95643f5218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570099449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2570099449
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3624739499
Short name T284
Test name
Test status
Simulation time 88685431 ps
CPU time 1.91 seconds
Started Aug 19 05:23:43 PM PDT 24
Finished Aug 19 05:23:45 PM PDT 24
Peak memory 197264 kb
Host smart-cee93e07-b46c-456f-ac56-ae1591f1626e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624739499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3624739499
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.878473977
Short name T414
Test name
Test status
Simulation time 40125167 ps
CPU time 1.37 seconds
Started Aug 19 05:23:44 PM PDT 24
Finished Aug 19 05:23:45 PM PDT 24
Peak memory 196944 kb
Host smart-e0137b77-9c51-498a-8840-74f06795e6a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878473977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
878473977
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1331777584
Short name T359
Test name
Test status
Simulation time 143236665 ps
CPU time 0.98 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 195972 kb
Host smart-46eb6700-b4bf-4b9b-918e-c96804a9fce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331777584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1331777584
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.375299715
Short name T417
Test name
Test status
Simulation time 519671484 ps
CPU time 1.3 seconds
Started Aug 19 05:23:40 PM PDT 24
Finished Aug 19 05:23:41 PM PDT 24
Peak memory 195908 kb
Host smart-82e01c5f-d604-4057-acd9-92028437fa62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375299715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.375299715
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.315975903
Short name T316
Test name
Test status
Simulation time 84532045 ps
CPU time 1.67 seconds
Started Aug 19 05:23:40 PM PDT 24
Finished Aug 19 05:23:42 PM PDT 24
Peak memory 198208 kb
Host smart-c6524503-2af1-4a9e-b250-200104a401fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315975903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.315975903
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1174681814
Short name T546
Test name
Test status
Simulation time 253887844 ps
CPU time 1.26 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 197012 kb
Host smart-ebf32570-309e-49b6-8f09-4ce17c99c790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174681814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1174681814
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.678153926
Short name T381
Test name
Test status
Simulation time 240149719 ps
CPU time 1.34 seconds
Started Aug 19 05:23:40 PM PDT 24
Finished Aug 19 05:23:41 PM PDT 24
Peak memory 196104 kb
Host smart-fde7c6d0-ce0b-486d-bf1b-081fb14345bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678153926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.678153926
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1117946479
Short name T329
Test name
Test status
Simulation time 4901806717 ps
CPU time 75.83 seconds
Started Aug 19 05:23:40 PM PDT 24
Finished Aug 19 05:24:56 PM PDT 24
Peak memory 198348 kb
Host smart-8abd0c43-8f18-4420-92a4-1188b715a5fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117946479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1117946479
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.252771197
Short name T60
Test name
Test status
Simulation time 5805565674 ps
CPU time 109.47 seconds
Started Aug 19 05:23:39 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 198540 kb
Host smart-800a7cee-24f8-4694-ad1d-b1f9026a2768
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=252771197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.252771197
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2173581589
Short name T325
Test name
Test status
Simulation time 38230027 ps
CPU time 0.6 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:54 PM PDT 24
Peak memory 194772 kb
Host smart-8ff3c501-8003-4384-b214-730bc568e7dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173581589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2173581589
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1144125716
Short name T635
Test name
Test status
Simulation time 53273154 ps
CPU time 0.95 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 195856 kb
Host smart-8a4b1b98-c8f6-42fe-ae39-d41e40f72f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144125716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1144125716
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2439954887
Short name T627
Test name
Test status
Simulation time 363424027 ps
CPU time 18.59 seconds
Started Aug 19 05:23:44 PM PDT 24
Finished Aug 19 05:24:03 PM PDT 24
Peak memory 196820 kb
Host smart-ea9fe77a-5a64-4fa1-82eb-42e934b1ae8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439954887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2439954887
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1715360922
Short name T402
Test name
Test status
Simulation time 80512226 ps
CPU time 0.79 seconds
Started Aug 19 05:24:01 PM PDT 24
Finished Aug 19 05:24:02 PM PDT 24
Peak memory 195960 kb
Host smart-f7f27c00-d489-4f67-bb5a-df53147516b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715360922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1715360922
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.530853284
Short name T683
Test name
Test status
Simulation time 119486857 ps
CPU time 1.02 seconds
Started Aug 19 05:23:45 PM PDT 24
Finished Aug 19 05:23:46 PM PDT 24
Peak memory 196072 kb
Host smart-18817f3f-a163-4016-bccf-dce6e69e531d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530853284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.530853284
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3449331810
Short name T232
Test name
Test status
Simulation time 63510464 ps
CPU time 2.66 seconds
Started Aug 19 05:23:44 PM PDT 24
Finished Aug 19 05:23:46 PM PDT 24
Peak memory 198124 kb
Host smart-64503d85-cc95-471e-bc76-4eb0363c9b64
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449331810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3449331810
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3259127375
Short name T481
Test name
Test status
Simulation time 154274492 ps
CPU time 3.67 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:46 PM PDT 24
Peak memory 197344 kb
Host smart-fc760d90-29f6-46bf-83f4-cf62afbbbcd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259127375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3259127375
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.4221718151
Short name T282
Test name
Test status
Simulation time 29088986 ps
CPU time 1.15 seconds
Started Aug 19 05:23:43 PM PDT 24
Finished Aug 19 05:23:44 PM PDT 24
Peak memory 196280 kb
Host smart-7ed945c4-750a-4a9a-98b6-1f991294efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221718151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.4221718151
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3299624339
Short name T201
Test name
Test status
Simulation time 92935419 ps
CPU time 1.17 seconds
Started Aug 19 05:23:44 PM PDT 24
Finished Aug 19 05:23:45 PM PDT 24
Peak memory 195988 kb
Host smart-7250236e-76f9-4640-bd81-64f4c9deaf89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299624339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3299624339
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.15182197
Short name T698
Test name
Test status
Simulation time 1006906369 ps
CPU time 4.96 seconds
Started Aug 19 05:23:55 PM PDT 24
Finished Aug 19 05:24:00 PM PDT 24
Peak memory 198220 kb
Host smart-2165c610-14bb-4bb7-94a6-3df176f6df8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15182197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand
om_long_reg_writes_reg_reads.15182197
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.4289602680
Short name T120
Test name
Test status
Simulation time 132002468 ps
CPU time 1.23 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:44 PM PDT 24
Peak memory 195716 kb
Host smart-c215242e-5a1e-460c-9975-35f149ab0da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289602680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.4289602680
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2764569950
Short name T117
Test name
Test status
Simulation time 30691473 ps
CPU time 0.94 seconds
Started Aug 19 05:23:42 PM PDT 24
Finished Aug 19 05:23:43 PM PDT 24
Peak memory 196592 kb
Host smart-383c2b37-4ba9-4a34-99ad-432429e0a22f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764569950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2764569950
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1839134973
Short name T365
Test name
Test status
Simulation time 4044210288 ps
CPU time 54.69 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:24:49 PM PDT 24
Peak memory 198360 kb
Host smart-a11c8602-5f09-418e-8e88-6cfbdb34ecd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839134973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1839134973
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3142362777
Short name T248
Test name
Test status
Simulation time 1065064925 ps
CPU time 40.65 seconds
Started Aug 19 05:23:52 PM PDT 24
Finished Aug 19 05:24:33 PM PDT 24
Peak memory 198312 kb
Host smart-d50c93a8-cef2-486c-a3ae-2487e0bf8fc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3142362777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3142362777
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2426583815
Short name T672
Test name
Test status
Simulation time 35776216 ps
CPU time 0.58 seconds
Started Aug 19 05:23:52 PM PDT 24
Finished Aug 19 05:23:53 PM PDT 24
Peak memory 194796 kb
Host smart-f268bc77-2f2e-4332-be2d-0d41ee7fe599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426583815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2426583815
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2945253708
Short name T558
Test name
Test status
Simulation time 167633245 ps
CPU time 0.96 seconds
Started Aug 19 05:23:52 PM PDT 24
Finished Aug 19 05:23:53 PM PDT 24
Peak memory 196932 kb
Host smart-b6e27caa-9a0d-4bac-b107-f4956dc14089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945253708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2945253708
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.570340541
Short name T136
Test name
Test status
Simulation time 1442770944 ps
CPU time 24.58 seconds
Started Aug 19 05:23:59 PM PDT 24
Finished Aug 19 05:24:24 PM PDT 24
Peak memory 197056 kb
Host smart-87b00375-e443-4682-ac84-0153f3b4cc71
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570340541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.570340541
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1019218281
Short name T266
Test name
Test status
Simulation time 50228195 ps
CPU time 0.81 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:23:54 PM PDT 24
Peak memory 196840 kb
Host smart-00b628f5-b15f-485a-aa4d-b263b095426d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019218281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1019218281
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3708586599
Short name T509
Test name
Test status
Simulation time 82579996 ps
CPU time 1.31 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 196308 kb
Host smart-87aeae1e-ce29-4c89-9663-b6e5a8ab0c8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708586599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3708586599
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3792638036
Short name T691
Test name
Test status
Simulation time 45883314 ps
CPU time 1.88 seconds
Started Aug 19 05:23:52 PM PDT 24
Finished Aug 19 05:23:54 PM PDT 24
Peak memory 198232 kb
Host smart-67e4a5e5-bd0f-441b-a9bc-bd1f3d223d81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792638036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3792638036
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3281325034
Short name T705
Test name
Test status
Simulation time 304018337 ps
CPU time 1.96 seconds
Started Aug 19 05:23:56 PM PDT 24
Finished Aug 19 05:23:58 PM PDT 24
Peak memory 196384 kb
Host smart-89855756-481e-424d-addc-d0b77992ac5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281325034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3281325034
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3268213734
Short name T688
Test name
Test status
Simulation time 193312606 ps
CPU time 1.18 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 198260 kb
Host smart-6c754665-7fc0-42cc-adf1-80750a823ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268213734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3268213734
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3034513599
Short name T104
Test name
Test status
Simulation time 175349941 ps
CPU time 1.08 seconds
Started Aug 19 05:23:51 PM PDT 24
Finished Aug 19 05:23:52 PM PDT 24
Peak memory 195976 kb
Host smart-1cb73c53-d076-402f-be96-515c08010aff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034513599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3034513599
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1612525512
Short name T239
Test name
Test status
Simulation time 410841338 ps
CPU time 6.55 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:24:01 PM PDT 24
Peak memory 198132 kb
Host smart-ab201e52-6f09-43f0-8492-c8ea985c32e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612525512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1612525512
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.94241998
Short name T697
Test name
Test status
Simulation time 80235198 ps
CPU time 1.27 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:55 PM PDT 24
Peak memory 196120 kb
Host smart-bbb9a2a9-2ea2-4422-902e-65a42445c6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94241998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.94241998
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1531988282
Short name T115
Test name
Test status
Simulation time 72372504 ps
CPU time 1.24 seconds
Started Aug 19 05:23:52 PM PDT 24
Finished Aug 19 05:23:53 PM PDT 24
Peak memory 195904 kb
Host smart-dc9da794-bb02-45af-abd1-dd286abd197c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531988282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1531988282
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1180812544
Short name T405
Test name
Test status
Simulation time 19126531570 ps
CPU time 177.57 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:26:52 PM PDT 24
Peak memory 198380 kb
Host smart-70300e0f-64f0-4a05-8ecc-c2067dcb721f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180812544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1180812544
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.651887768
Short name T286
Test name
Test status
Simulation time 24954063 ps
CPU time 0.56 seconds
Started Aug 19 05:22:27 PM PDT 24
Finished Aug 19 05:22:28 PM PDT 24
Peak memory 194096 kb
Host smart-812a9b12-623b-4060-9d52-bbcd3f44e074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651887768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.651887768
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.448582200
Short name T388
Test name
Test status
Simulation time 61188202 ps
CPU time 0.79 seconds
Started Aug 19 05:22:19 PM PDT 24
Finished Aug 19 05:22:20 PM PDT 24
Peak memory 195504 kb
Host smart-7ff41c58-bf22-46bb-8c5a-c53de14b36d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448582200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.448582200
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3019366547
Short name T169
Test name
Test status
Simulation time 2230298515 ps
CPU time 17.26 seconds
Started Aug 19 05:22:26 PM PDT 24
Finished Aug 19 05:22:44 PM PDT 24
Peak memory 198268 kb
Host smart-cca0117c-ec53-4c36-af1b-048a922ebc2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019366547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3019366547
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3836556544
Short name T522
Test name
Test status
Simulation time 567731656 ps
CPU time 0.93 seconds
Started Aug 19 05:22:24 PM PDT 24
Finished Aug 19 05:22:25 PM PDT 24
Peak memory 196712 kb
Host smart-ec2bb379-feb6-4609-a829-940882c5fdaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836556544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3836556544
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.784305537
Short name T221
Test name
Test status
Simulation time 179190216 ps
CPU time 1.19 seconds
Started Aug 19 05:22:25 PM PDT 24
Finished Aug 19 05:22:26 PM PDT 24
Peak memory 197316 kb
Host smart-6a69a9bb-a602-4453-860d-7a3c5804ff6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784305537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.784305537
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2397657824
Short name T347
Test name
Test status
Simulation time 58637616 ps
CPU time 2.38 seconds
Started Aug 19 05:22:27 PM PDT 24
Finished Aug 19 05:22:29 PM PDT 24
Peak memory 198260 kb
Host smart-da5cba2f-ad5d-41a2-b38d-8217cbc24af2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397657824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2397657824
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3926901149
Short name T292
Test name
Test status
Simulation time 473156075 ps
CPU time 3.57 seconds
Started Aug 19 05:22:25 PM PDT 24
Finished Aug 19 05:22:28 PM PDT 24
Peak memory 197132 kb
Host smart-ca75166c-366f-497b-871a-20ea5cb2a8a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926901149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3926901149
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2296577079
Short name T355
Test name
Test status
Simulation time 62714015 ps
CPU time 1.34 seconds
Started Aug 19 05:22:16 PM PDT 24
Finished Aug 19 05:22:18 PM PDT 24
Peak memory 197228 kb
Host smart-8223c974-e01c-44cf-9257-363d591c3bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296577079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2296577079
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2139121621
Short name T391
Test name
Test status
Simulation time 47292338 ps
CPU time 1.01 seconds
Started Aug 19 05:22:18 PM PDT 24
Finished Aug 19 05:22:19 PM PDT 24
Peak memory 196232 kb
Host smart-12da0f0f-bed3-4bfb-a0b8-ff462f495124
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139121621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2139121621
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.218585572
Short name T565
Test name
Test status
Simulation time 696964947 ps
CPU time 6.24 seconds
Started Aug 19 05:22:25 PM PDT 24
Finished Aug 19 05:22:31 PM PDT 24
Peak memory 198216 kb
Host smart-1393d099-e661-4787-b7f7-5bdbb2e9bb5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218585572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.218585572
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.509659967
Short name T49
Test name
Test status
Simulation time 2151013084 ps
CPU time 0.97 seconds
Started Aug 19 05:22:26 PM PDT 24
Finished Aug 19 05:22:27 PM PDT 24
Peak memory 215180 kb
Host smart-e559ab0a-cce6-4f0c-ac4c-6d9f1f79339e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509659967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.509659967
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3753776439
Short name T470
Test name
Test status
Simulation time 39557158 ps
CPU time 0.88 seconds
Started Aug 19 05:22:18 PM PDT 24
Finished Aug 19 05:22:19 PM PDT 24
Peak memory 195460 kb
Host smart-69908e8d-d055-49eb-9dd9-59bfc1c9c52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753776439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3753776439
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2779495821
Short name T116
Test name
Test status
Simulation time 44231253 ps
CPU time 1.34 seconds
Started Aug 19 05:22:19 PM PDT 24
Finished Aug 19 05:22:20 PM PDT 24
Peak memory 196780 kb
Host smart-8ad52498-3439-422a-a708-4f6bcc2d78b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779495821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2779495821
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1519011481
Short name T592
Test name
Test status
Simulation time 49850243450 ps
CPU time 177.16 seconds
Started Aug 19 05:22:25 PM PDT 24
Finished Aug 19 05:25:22 PM PDT 24
Peak memory 198388 kb
Host smart-cd351453-ec6b-49c1-b1c5-cc8213905f24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519011481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1519011481
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2503940721
Short name T478
Test name
Test status
Simulation time 18695700 ps
CPU time 0.6 seconds
Started Aug 19 05:23:56 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 194080 kb
Host smart-b14eeeb0-8f9d-4f2e-a8ed-d8dd0da7d5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503940721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2503940721
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1876466276
Short name T462
Test name
Test status
Simulation time 95211736 ps
CPU time 0.96 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:23:55 PM PDT 24
Peak memory 196116 kb
Host smart-85dac67a-5f6d-4d60-b73d-c7e9bb32a142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876466276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1876466276
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3398487669
Short name T100
Test name
Test status
Simulation time 1650483613 ps
CPU time 11.78 seconds
Started Aug 19 05:23:55 PM PDT 24
Finished Aug 19 05:24:07 PM PDT 24
Peak memory 198208 kb
Host smart-ad80eeb4-dece-4ecd-b236-5a1634fb1685
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398487669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3398487669
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1097149429
Short name T700
Test name
Test status
Simulation time 273095423 ps
CPU time 1 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:55 PM PDT 24
Peak memory 198136 kb
Host smart-dbba8ac2-5358-41b2-aa6f-8cd11b8065d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097149429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1097149429
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1223316575
Short name T249
Test name
Test status
Simulation time 38579365 ps
CPU time 1.23 seconds
Started Aug 19 05:23:55 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 196312 kb
Host smart-90bb9cd9-1d19-40a7-96cf-85aa428c6795
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223316575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1223316575
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3897323787
Short name T247
Test name
Test status
Simulation time 184392420 ps
CPU time 3.79 seconds
Started Aug 19 05:24:00 PM PDT 24
Finished Aug 19 05:24:04 PM PDT 24
Peak memory 198228 kb
Host smart-75eea9c8-0c81-4421-b135-620d87221e5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897323787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3897323787
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.209158780
Short name T653
Test name
Test status
Simulation time 355456487 ps
CPU time 2.85 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 196900 kb
Host smart-25c3f4b0-6f07-409b-93c5-255782e6b0c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209158780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
209158780
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3218202324
Short name T308
Test name
Test status
Simulation time 109033582 ps
CPU time 0.75 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:23:54 PM PDT 24
Peak memory 194568 kb
Host smart-e1cf70ec-390f-4c00-bf30-df42874b4df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218202324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3218202324
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3874420859
Short name T175
Test name
Test status
Simulation time 32445895 ps
CPU time 0.8 seconds
Started Aug 19 05:24:00 PM PDT 24
Finished Aug 19 05:24:01 PM PDT 24
Peak memory 195688 kb
Host smart-592bf609-392e-4b65-a9f4-bb9691916a29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874420859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3874420859
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3022221151
Short name T256
Test name
Test status
Simulation time 1368254265 ps
CPU time 6.01 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:23:59 PM PDT 24
Peak memory 198192 kb
Host smart-88bc3b1e-a40c-410a-9798-9624f36c1155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022221151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3022221151
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2212857173
Short name T518
Test name
Test status
Simulation time 616348578 ps
CPU time 1.14 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:23:54 PM PDT 24
Peak memory 196612 kb
Host smart-ab1bf181-e439-4ffb-9613-b94af10967d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212857173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2212857173
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2045130984
Short name T164
Test name
Test status
Simulation time 99858338 ps
CPU time 1.22 seconds
Started Aug 19 05:23:51 PM PDT 24
Finished Aug 19 05:23:53 PM PDT 24
Peak memory 196048 kb
Host smart-4ac32711-4d20-4041-a561-fa1314639f8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045130984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2045130984
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1712220489
Short name T165
Test name
Test status
Simulation time 292828347862 ps
CPU time 206.76 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:27:19 PM PDT 24
Peak memory 198364 kb
Host smart-dbe99633-cdc5-4717-88e5-cf5d02b8a60d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712220489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1712220489
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.4103628780
Short name T399
Test name
Test status
Simulation time 5186554056 ps
CPU time 162.46 seconds
Started Aug 19 05:23:50 PM PDT 24
Finished Aug 19 05:26:33 PM PDT 24
Peak memory 198548 kb
Host smart-e03d9125-b658-4fda-a774-c6ecba53d5da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4103628780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.4103628780
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2908191597
Short name T463
Test name
Test status
Simulation time 23301157 ps
CPU time 0.56 seconds
Started Aug 19 05:23:57 PM PDT 24
Finished Aug 19 05:23:58 PM PDT 24
Peak memory 194032 kb
Host smart-b254161f-38ba-434c-9da3-be6fced26a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908191597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2908191597
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.23888395
Short name T663
Test name
Test status
Simulation time 20830953 ps
CPU time 0.7 seconds
Started Aug 19 05:23:52 PM PDT 24
Finished Aug 19 05:23:52 PM PDT 24
Peak memory 194224 kb
Host smart-ac3dbdaf-8c60-4814-b2fc-a62b59b02f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23888395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.23888395
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1001779926
Short name T706
Test name
Test status
Simulation time 1801926504 ps
CPU time 22.75 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:24:17 PM PDT 24
Peak memory 198156 kb
Host smart-c7e68f85-2cf3-411b-8292-952077201cc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001779926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1001779926
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3155728047
Short name T686
Test name
Test status
Simulation time 149030455 ps
CPU time 0.93 seconds
Started Aug 19 05:23:57 PM PDT 24
Finished Aug 19 05:23:58 PM PDT 24
Peak memory 196104 kb
Host smart-4fd62e25-f4fc-479a-93da-50e7a0f2d20b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155728047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3155728047
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2518612137
Short name T709
Test name
Test status
Simulation time 140968207 ps
CPU time 1.19 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 196336 kb
Host smart-99bd971e-19ec-4571-bf81-561e9b0a7aa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518612137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2518612137
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3625563452
Short name T581
Test name
Test status
Simulation time 21144155 ps
CPU time 1.06 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:55 PM PDT 24
Peak memory 197004 kb
Host smart-f95c34ec-8ddb-4627-84a9-fb6f42276748
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625563452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3625563452
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3421842975
Short name T423
Test name
Test status
Simulation time 1136867788 ps
CPU time 2.55 seconds
Started Aug 19 05:23:55 PM PDT 24
Finished Aug 19 05:23:58 PM PDT 24
Peak memory 195992 kb
Host smart-106aed63-8295-48ef-8bf8-3015ffa76eb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421842975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3421842975
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3408334912
Short name T585
Test name
Test status
Simulation time 20936891 ps
CPU time 0.91 seconds
Started Aug 19 05:23:55 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 197368 kb
Host smart-756b99bb-5a67-4477-b423-952321eb2910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408334912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3408334912
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3625193028
Short name T276
Test name
Test status
Simulation time 29091092 ps
CPU time 0.84 seconds
Started Aug 19 05:23:51 PM PDT 24
Finished Aug 19 05:23:52 PM PDT 24
Peak memory 196276 kb
Host smart-cdde69d6-ab47-4868-9920-75dd9b4401e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625193028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3625193028
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2815372489
Short name T357
Test name
Test status
Simulation time 250002183 ps
CPU time 5.92 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:24:00 PM PDT 24
Peak memory 198184 kb
Host smart-c30eda49-c2d7-4e36-89f9-975743673fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815372489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2815372489
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.110198452
Short name T617
Test name
Test status
Simulation time 43277339 ps
CPU time 0.81 seconds
Started Aug 19 05:23:53 PM PDT 24
Finished Aug 19 05:23:54 PM PDT 24
Peak memory 196056 kb
Host smart-67901acc-b4ac-4085-824b-b9b70f36633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110198452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.110198452
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3843726799
Short name T130
Test name
Test status
Simulation time 213387417 ps
CPU time 1.18 seconds
Started Aug 19 05:23:54 PM PDT 24
Finished Aug 19 05:23:56 PM PDT 24
Peak memory 195996 kb
Host smart-58752351-644e-4784-aebd-9cedd6da234a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843726799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3843726799
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.219162446
Short name T395
Test name
Test status
Simulation time 9508977391 ps
CPU time 140.14 seconds
Started Aug 19 05:23:56 PM PDT 24
Finished Aug 19 05:26:16 PM PDT 24
Peak memory 198336 kb
Host smart-9f80a6e2-7b96-4e60-b66d-03434db5a655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219162446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.219162446
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1019969600
Short name T375
Test name
Test status
Simulation time 13993419686 ps
CPU time 234.79 seconds
Started Aug 19 05:24:00 PM PDT 24
Finished Aug 19 05:27:55 PM PDT 24
Peak memory 198552 kb
Host smart-f7b95272-ef5d-4b3e-b443-e92b62c3e346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1019969600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1019969600
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.877202406
Short name T584
Test name
Test status
Simulation time 40347905 ps
CPU time 0.58 seconds
Started Aug 19 05:23:59 PM PDT 24
Finished Aug 19 05:24:00 PM PDT 24
Peak memory 194056 kb
Host smart-25ddc49d-b6f2-40d0-bc87-ea87dde12e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877202406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.877202406
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.479834097
Short name T160
Test name
Test status
Simulation time 34100218 ps
CPU time 0.77 seconds
Started Aug 19 05:23:58 PM PDT 24
Finished Aug 19 05:23:59 PM PDT 24
Peak memory 195700 kb
Host smart-6fa933c6-3ba3-4a59-821a-394333abc3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479834097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.479834097
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2360354459
Short name T714
Test name
Test status
Simulation time 611320335 ps
CPU time 17.28 seconds
Started Aug 19 05:24:01 PM PDT 24
Finished Aug 19 05:24:19 PM PDT 24
Peak memory 197020 kb
Host smart-a1928025-cb39-44d3-9e45-5120de0d5605
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360354459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2360354459
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.908369538
Short name T582
Test name
Test status
Simulation time 38688716 ps
CPU time 0.66 seconds
Started Aug 19 05:23:57 PM PDT 24
Finished Aug 19 05:23:58 PM PDT 24
Peak memory 195368 kb
Host smart-f1b9f994-d404-4617-b7e0-57eaca04686d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908369538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.908369538
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3155852574
Short name T400
Test name
Test status
Simulation time 145938284 ps
CPU time 1.11 seconds
Started Aug 19 05:23:56 PM PDT 24
Finished Aug 19 05:23:57 PM PDT 24
Peak memory 195944 kb
Host smart-c8ae9a10-2922-44af-9f8e-52fea82b248c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155852574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3155852574
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2135820150
Short name T354
Test name
Test status
Simulation time 129729439 ps
CPU time 2.88 seconds
Started Aug 19 05:24:01 PM PDT 24
Finished Aug 19 05:24:04 PM PDT 24
Peak memory 198200 kb
Host smart-3c7e890a-5d5f-4a81-b347-076ac959d275
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135820150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2135820150
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4149088155
Short name T114
Test name
Test status
Simulation time 211942815 ps
CPU time 1.47 seconds
Started Aug 19 05:23:58 PM PDT 24
Finished Aug 19 05:24:00 PM PDT 24
Peak memory 195952 kb
Host smart-57013639-c559-4142-832e-7cc54361a2d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149088155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4149088155
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2838286084
Short name T528
Test name
Test status
Simulation time 115135767 ps
CPU time 0.84 seconds
Started Aug 19 05:23:57 PM PDT 24
Finished Aug 19 05:23:58 PM PDT 24
Peak memory 196404 kb
Host smart-4afaccdf-0d59-436b-9073-070be4582847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838286084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2838286084
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2392406632
Short name T556
Test name
Test status
Simulation time 291836215 ps
CPU time 1.05 seconds
Started Aug 19 05:24:01 PM PDT 24
Finished Aug 19 05:24:02 PM PDT 24
Peak memory 196952 kb
Host smart-a8f30a40-454c-4177-8cf2-aec7c04d3ddd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392406632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2392406632
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1243232752
Short name T319
Test name
Test status
Simulation time 480651950 ps
CPU time 2.87 seconds
Started Aug 19 05:24:00 PM PDT 24
Finished Aug 19 05:24:02 PM PDT 24
Peak memory 198184 kb
Host smart-62261237-f2e4-4da3-9574-96507248248d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243232752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1243232752
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3859789044
Short name T413
Test name
Test status
Simulation time 297854254 ps
CPU time 1.63 seconds
Started Aug 19 05:23:58 PM PDT 24
Finished Aug 19 05:24:00 PM PDT 24
Peak memory 198160 kb
Host smart-af2c63e3-2e41-412d-b04e-f50c6c2f2d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859789044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3859789044
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1410300339
Short name T55
Test name
Test status
Simulation time 62525074 ps
CPU time 1.01 seconds
Started Aug 19 05:24:00 PM PDT 24
Finished Aug 19 05:24:01 PM PDT 24
Peak memory 196064 kb
Host smart-a502d8a7-621a-4746-a1b6-576720644407
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410300339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1410300339
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4209944847
Short name T517
Test name
Test status
Simulation time 6048738151 ps
CPU time 162.17 seconds
Started Aug 19 05:23:58 PM PDT 24
Finished Aug 19 05:26:40 PM PDT 24
Peak memory 192248 kb
Host smart-2e97fabd-57d7-4ee2-9911-68ead98d0be9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209944847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4209944847
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1776268470
Short name T27
Test name
Test status
Simulation time 15641359136 ps
CPU time 138.07 seconds
Started Aug 19 05:23:58 PM PDT 24
Finished Aug 19 05:26:16 PM PDT 24
Peak memory 198564 kb
Host smart-1f7d1e1d-321c-4207-846c-dd653a5c4e4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1776268470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1776268470
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.244826154
Short name T692
Test name
Test status
Simulation time 13709451 ps
CPU time 0.61 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:24:08 PM PDT 24
Peak memory 195812 kb
Host smart-6deb88e1-ae1c-4f0d-b032-b2192119ed58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244826154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.244826154
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3930279249
Short name T474
Test name
Test status
Simulation time 41517900 ps
CPU time 0.75 seconds
Started Aug 19 05:24:10 PM PDT 24
Finished Aug 19 05:24:11 PM PDT 24
Peak memory 195420 kb
Host smart-719bdfe3-5b88-4e69-9de3-e1f0a5528d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930279249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3930279249
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.446737299
Short name T333
Test name
Test status
Simulation time 1874072504 ps
CPU time 12.03 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:24:19 PM PDT 24
Peak memory 197000 kb
Host smart-81048db3-1001-4559-8d90-5f5ceec8fdba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446737299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.446737299
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.369023026
Short name T56
Test name
Test status
Simulation time 19706183 ps
CPU time 0.66 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:24:08 PM PDT 24
Peak memory 194580 kb
Host smart-edafb351-81d4-4962-a7b4-04cf45827b15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369023026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.369023026
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3748396555
Short name T215
Test name
Test status
Simulation time 96790735 ps
CPU time 0.9 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:24:08 PM PDT 24
Peak memory 196896 kb
Host smart-e3646adf-07e8-4dc1-9c10-b460c3d91531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748396555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3748396555
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.4095416929
Short name T397
Test name
Test status
Simulation time 127453891 ps
CPU time 2.56 seconds
Started Aug 19 05:24:06 PM PDT 24
Finished Aug 19 05:24:09 PM PDT 24
Peak memory 198188 kb
Host smart-7965f105-7c96-4f5f-a60d-53a2b6e81d3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095416929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.4095416929
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3058654077
Short name T360
Test name
Test status
Simulation time 153818239 ps
CPU time 2.79 seconds
Started Aug 19 05:24:06 PM PDT 24
Finished Aug 19 05:24:09 PM PDT 24
Peak memory 198232 kb
Host smart-cc411034-c1f4-4f89-8b96-cdc9520ef9e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058654077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3058654077
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2207434570
Short name T614
Test name
Test status
Simulation time 669234066 ps
CPU time 1.31 seconds
Started Aug 19 05:24:00 PM PDT 24
Finished Aug 19 05:24:02 PM PDT 24
Peak memory 197172 kb
Host smart-20ba966f-783e-4fcf-a0a6-b77c4fce7ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207434570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2207434570
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1317635068
Short name T386
Test name
Test status
Simulation time 54024585 ps
CPU time 1.27 seconds
Started Aug 19 05:24:01 PM PDT 24
Finished Aug 19 05:24:02 PM PDT 24
Peak memory 198240 kb
Host smart-38d45789-7a91-45d5-bfa2-151dbc14d2e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317635068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1317635068
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2599711913
Short name T408
Test name
Test status
Simulation time 204823916 ps
CPU time 3.46 seconds
Started Aug 19 05:24:08 PM PDT 24
Finished Aug 19 05:24:12 PM PDT 24
Peak memory 197424 kb
Host smart-53bbdf1c-05af-43da-8438-934f417e43a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599711913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2599711913
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2053033172
Short name T668
Test name
Test status
Simulation time 55599009 ps
CPU time 1.17 seconds
Started Aug 19 05:23:57 PM PDT 24
Finished Aug 19 05:23:59 PM PDT 24
Peak memory 196752 kb
Host smart-114cca37-ac7f-4eaa-acce-67e94b004004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053033172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2053033172
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1884839856
Short name T538
Test name
Test status
Simulation time 205599488 ps
CPU time 0.96 seconds
Started Aug 19 05:23:59 PM PDT 24
Finished Aug 19 05:24:00 PM PDT 24
Peak memory 195856 kb
Host smart-8b427498-564a-446d-bf8a-a1e32fbcad13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884839856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1884839856
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2662936299
Short name T680
Test name
Test status
Simulation time 15620631461 ps
CPU time 195.7 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:27:22 PM PDT 24
Peak memory 198392 kb
Host smart-98ced3cb-5c09-46a4-8908-d9c8975a0896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662936299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2662936299
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1120090891
Short name T416
Test name
Test status
Simulation time 1982845324 ps
CPU time 64.95 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:25:12 PM PDT 24
Peak memory 198412 kb
Host smart-07b70b29-edd1-485b-adfb-3523cd9e775a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1120090891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1120090891
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1528954367
Short name T428
Test name
Test status
Simulation time 40958438 ps
CPU time 0.58 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:16 PM PDT 24
Peak memory 194088 kb
Host smart-9f56e367-8c6c-4c8e-b2ef-fc5d59ce3429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528954367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1528954367
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.307485993
Short name T562
Test name
Test status
Simulation time 49749084 ps
CPU time 0.6 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:24:08 PM PDT 24
Peak memory 194120 kb
Host smart-f75b6375-99b1-4264-985c-722b360a8db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307485993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.307485993
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2975073448
Short name T371
Test name
Test status
Simulation time 208724396 ps
CPU time 5.95 seconds
Started Aug 19 05:24:08 PM PDT 24
Finished Aug 19 05:24:14 PM PDT 24
Peak memory 197168 kb
Host smart-750d6ca4-ba0d-4e77-aee8-14599deb11db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975073448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2975073448
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1863116646
Short name T593
Test name
Test status
Simulation time 127379124 ps
CPU time 0.65 seconds
Started Aug 19 05:24:10 PM PDT 24
Finished Aug 19 05:24:11 PM PDT 24
Peak memory 194696 kb
Host smart-89e7f91d-2b4d-473e-9c11-659898a49dd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863116646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1863116646
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3179835107
Short name T305
Test name
Test status
Simulation time 298661068 ps
CPU time 1.17 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:24:08 PM PDT 24
Peak memory 196208 kb
Host smart-d9b2cc2f-e610-44b8-8460-5284b92969c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179835107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3179835107
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1566346056
Short name T126
Test name
Test status
Simulation time 235743890 ps
CPU time 2.51 seconds
Started Aug 19 05:24:10 PM PDT 24
Finished Aug 19 05:24:12 PM PDT 24
Peak memory 196596 kb
Host smart-83c7e8e5-9a5b-4dc5-b4e7-ea699ad52b5e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566346056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1566346056
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1121772052
Short name T567
Test name
Test status
Simulation time 409455961 ps
CPU time 2.38 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:24:09 PM PDT 24
Peak memory 197340 kb
Host smart-8795b38f-37af-4827-b65c-7ec002d2bb39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121772052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1121772052
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2317429813
Short name T612
Test name
Test status
Simulation time 61338743 ps
CPU time 0.89 seconds
Started Aug 19 05:24:09 PM PDT 24
Finished Aug 19 05:24:10 PM PDT 24
Peak memory 196232 kb
Host smart-dc88b05d-9330-449c-b56c-01da582f3096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317429813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2317429813
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.383038703
Short name T390
Test name
Test status
Simulation time 285723256 ps
CPU time 0.92 seconds
Started Aug 19 05:24:09 PM PDT 24
Finished Aug 19 05:24:10 PM PDT 24
Peak memory 195984 kb
Host smart-b5caff2d-1772-4587-ae1e-e9a5f5cdd4cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383038703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.383038703
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.973107890
Short name T564
Test name
Test status
Simulation time 209140286 ps
CPU time 4.76 seconds
Started Aug 19 05:24:08 PM PDT 24
Finished Aug 19 05:24:13 PM PDT 24
Peak memory 198168 kb
Host smart-80c50373-52bd-4e6f-979c-9ecf1e8f12df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973107890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.973107890
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1919502606
Short name T335
Test name
Test status
Simulation time 36519405 ps
CPU time 1.04 seconds
Started Aug 19 05:24:10 PM PDT 24
Finished Aug 19 05:24:12 PM PDT 24
Peak memory 195952 kb
Host smart-9aeaf419-9d90-425c-8ad3-00da39c764ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919502606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1919502606
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.133893089
Short name T623
Test name
Test status
Simulation time 102855984 ps
CPU time 1.44 seconds
Started Aug 19 05:24:11 PM PDT 24
Finished Aug 19 05:24:12 PM PDT 24
Peak memory 197036 kb
Host smart-9ca1d37a-c5fc-449a-a1cf-2628e58d724a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133893089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.133893089
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.792874359
Short name T218
Test name
Test status
Simulation time 39229708231 ps
CPU time 144.8 seconds
Started Aug 19 05:24:07 PM PDT 24
Finished Aug 19 05:26:32 PM PDT 24
Peak memory 192000 kb
Host smart-7000b507-bf94-4e77-9b4e-5b4262218310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792874359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.792874359
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.499859558
Short name T39
Test name
Test status
Simulation time 15008217 ps
CPU time 0.59 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:17 PM PDT 24
Peak memory 194356 kb
Host smart-e88b49c6-a5f7-415a-8236-4dda04bad5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499859558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.499859558
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3655184372
Short name T467
Test name
Test status
Simulation time 19898886 ps
CPU time 0.71 seconds
Started Aug 19 05:24:17 PM PDT 24
Finished Aug 19 05:24:18 PM PDT 24
Peak memory 195416 kb
Host smart-08b8a7b1-fe77-47b1-9a1e-22cf77a57e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655184372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3655184372
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2230500468
Short name T578
Test name
Test status
Simulation time 184085991 ps
CPU time 9.34 seconds
Started Aug 19 05:24:15 PM PDT 24
Finished Aug 19 05:24:25 PM PDT 24
Peak memory 197052 kb
Host smart-651c398c-e280-4507-a3aa-10c2ce2147ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230500468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2230500468
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4103460429
Short name T674
Test name
Test status
Simulation time 98241068 ps
CPU time 0.84 seconds
Started Aug 19 05:24:20 PM PDT 24
Finished Aug 19 05:24:21 PM PDT 24
Peak memory 196624 kb
Host smart-cac90308-b69a-4d0b-a221-25e4e12388ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103460429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4103460429
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2907718762
Short name T624
Test name
Test status
Simulation time 66567807 ps
CPU time 1.16 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:18 PM PDT 24
Peak memory 197088 kb
Host smart-eabe6b1f-17e6-40dd-8df4-14e3b44000b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907718762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2907718762
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.812091835
Short name T403
Test name
Test status
Simulation time 63927548 ps
CPU time 0.96 seconds
Started Aug 19 05:24:22 PM PDT 24
Finished Aug 19 05:24:23 PM PDT 24
Peak memory 196152 kb
Host smart-f35ce351-27f0-4b33-8927-ad07b59bd665
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812091835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.812091835
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3077579970
Short name T679
Test name
Test status
Simulation time 155289564 ps
CPU time 3.05 seconds
Started Aug 19 05:24:15 PM PDT 24
Finished Aug 19 05:24:18 PM PDT 24
Peak memory 197100 kb
Host smart-4be2d72e-4511-430b-9526-ddb92d72aca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077579970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3077579970
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.4193059836
Short name T521
Test name
Test status
Simulation time 36385326 ps
CPU time 0.94 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:17 PM PDT 24
Peak memory 196744 kb
Host smart-c86433f1-0440-4a63-a5eb-24a0ca2ac879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193059836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.4193059836
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.567616221
Short name T278
Test name
Test status
Simulation time 63058655 ps
CPU time 1.29 seconds
Started Aug 19 05:24:21 PM PDT 24
Finished Aug 19 05:24:22 PM PDT 24
Peak memory 196028 kb
Host smart-948142e2-e826-4bdf-93b6-2b73a255e182
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567616221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.567616221
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.336482128
Short name T667
Test name
Test status
Simulation time 1018587625 ps
CPU time 3.27 seconds
Started Aug 19 05:24:21 PM PDT 24
Finished Aug 19 05:24:24 PM PDT 24
Peak memory 198012 kb
Host smart-22cd0c1d-8348-4222-9d2a-3e5682788959
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336482128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.336482128
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4022309873
Short name T605
Test name
Test status
Simulation time 113231147 ps
CPU time 1.05 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:20 PM PDT 24
Peak memory 195988 kb
Host smart-b9954d78-5e26-4265-8dd4-7b618f0d1600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022309873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4022309873
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4096222587
Short name T235
Test name
Test status
Simulation time 162412162 ps
CPU time 1.49 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:21 PM PDT 24
Peak memory 196440 kb
Host smart-26804347-0b54-4e85-970e-de79047dcaa4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096222587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4096222587
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3646390190
Short name T280
Test name
Test status
Simulation time 23202029425 ps
CPU time 164.81 seconds
Started Aug 19 05:24:17 PM PDT 24
Finished Aug 19 05:27:02 PM PDT 24
Peak memory 198356 kb
Host smart-d7bdff13-5f8c-4455-9e3d-32ea0fd1a973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646390190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3646390190
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1813779402
Short name T217
Test name
Test status
Simulation time 6716544075 ps
CPU time 101.92 seconds
Started Aug 19 05:24:21 PM PDT 24
Finished Aug 19 05:26:03 PM PDT 24
Peak memory 198548 kb
Host smart-0096de7c-8ca7-41e0-804d-f3d74e64402e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1813779402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1813779402
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3730834524
Short name T656
Test name
Test status
Simulation time 44103702 ps
CPU time 0.56 seconds
Started Aug 19 05:24:17 PM PDT 24
Finished Aug 19 05:24:18 PM PDT 24
Peak memory 194092 kb
Host smart-5bb1cf78-bf03-42c6-a207-60e47909020b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730834524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3730834524
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3242501295
Short name T575
Test name
Test status
Simulation time 19894561 ps
CPU time 0.61 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:19 PM PDT 24
Peak memory 194096 kb
Host smart-66161de7-aa07-4a66-926e-92c3f9e5bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242501295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3242501295
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2127946796
Short name T58
Test name
Test status
Simulation time 640156690 ps
CPU time 16.18 seconds
Started Aug 19 05:24:20 PM PDT 24
Finished Aug 19 05:24:36 PM PDT 24
Peak memory 197088 kb
Host smart-8605161f-bb4d-4414-a155-13da16565080
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127946796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2127946796
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.550756970
Short name T407
Test name
Test status
Simulation time 38669596 ps
CPU time 0.74 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:20 PM PDT 24
Peak memory 195640 kb
Host smart-8c78ac47-ac60-459d-a2fb-750ec1a59154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550756970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.550756970
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2867988676
Short name T343
Test name
Test status
Simulation time 72756869 ps
CPU time 1.18 seconds
Started Aug 19 05:24:20 PM PDT 24
Finished Aug 19 05:24:21 PM PDT 24
Peak memory 196960 kb
Host smart-0acb21ba-ecaa-4434-aafe-9b0b0580dc14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867988676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2867988676
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1028855057
Short name T421
Test name
Test status
Simulation time 91501067 ps
CPU time 1.91 seconds
Started Aug 19 05:24:17 PM PDT 24
Finished Aug 19 05:24:19 PM PDT 24
Peak memory 198084 kb
Host smart-b7e43855-2b84-40cc-bf81-3e748731ff3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028855057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1028855057
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4055909026
Short name T626
Test name
Test status
Simulation time 101513772 ps
CPU time 2.01 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:18 PM PDT 24
Peak memory 196260 kb
Host smart-d653176b-aebe-4010-b9c4-df09d55016ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055909026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4055909026
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3471988775
Short name T346
Test name
Test status
Simulation time 204312528 ps
CPU time 1.13 seconds
Started Aug 19 05:24:18 PM PDT 24
Finished Aug 19 05:24:20 PM PDT 24
Peak memory 196924 kb
Host smart-4bb9eec6-a40c-4afd-88f8-680a0b55367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471988775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3471988775
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3761398665
Short name T587
Test name
Test status
Simulation time 23553534 ps
CPU time 0.78 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:20 PM PDT 24
Peak memory 196252 kb
Host smart-151bf545-ce59-4c3e-9a86-698f28f2a04c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761398665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3761398665
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1455264135
Short name T681
Test name
Test status
Simulation time 5342674926 ps
CPU time 5.13 seconds
Started Aug 19 05:24:17 PM PDT 24
Finished Aug 19 05:24:22 PM PDT 24
Peak memory 198204 kb
Host smart-88693925-8257-4bdf-8a45-530b33e3ff10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455264135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1455264135
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2348413363
Short name T323
Test name
Test status
Simulation time 105025810 ps
CPU time 0.88 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:17 PM PDT 24
Peak memory 196056 kb
Host smart-e81cdeeb-7c6a-4308-911a-b07faedc6b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348413363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2348413363
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2008143502
Short name T24
Test name
Test status
Simulation time 89850800 ps
CPU time 0.9 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:20 PM PDT 24
Peak memory 196408 kb
Host smart-8b6eacdc-4f9b-4d04-98fc-c9b2e4ca57d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008143502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2008143502
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4070371098
Short name T550
Test name
Test status
Simulation time 14976318924 ps
CPU time 197.68 seconds
Started Aug 19 05:24:15 PM PDT 24
Finished Aug 19 05:27:33 PM PDT 24
Peak memory 198412 kb
Host smart-414f458a-cb62-4593-b9aa-96ac22ec2ef3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070371098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4070371098
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3060553690
Short name T455
Test name
Test status
Simulation time 23306443 ps
CPU time 0.58 seconds
Started Aug 19 05:24:27 PM PDT 24
Finished Aug 19 05:24:28 PM PDT 24
Peak memory 194056 kb
Host smart-73d7b3dc-d7c6-4e02-a018-bc53268e874f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060553690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3060553690
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.945740407
Short name T445
Test name
Test status
Simulation time 37647404 ps
CPU time 0.68 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:19 PM PDT 24
Peak memory 195428 kb
Host smart-4021f544-4957-47aa-8a18-40f3d4066b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945740407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.945740407
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.56617079
Short name T366
Test name
Test status
Simulation time 3244251257 ps
CPU time 16.75 seconds
Started Aug 19 05:24:19 PM PDT 24
Finished Aug 19 05:24:36 PM PDT 24
Peak memory 197632 kb
Host smart-6da4ba54-9bbd-4314-acb7-da196ca96a24
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56617079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.56617079
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1725330177
Short name T176
Test name
Test status
Simulation time 71194894 ps
CPU time 0.74 seconds
Started Aug 19 05:24:18 PM PDT 24
Finished Aug 19 05:24:19 PM PDT 24
Peak memory 194784 kb
Host smart-3dec167e-7596-413e-b2be-65dfb9d7ebb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725330177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1725330177
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.962453357
Short name T302
Test name
Test status
Simulation time 78573546 ps
CPU time 0.86 seconds
Started Aug 19 05:24:18 PM PDT 24
Finished Aug 19 05:24:19 PM PDT 24
Peak memory 195760 kb
Host smart-003ffd0b-29c7-480d-aefe-10cf9895801c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962453357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.962453357
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3912471646
Short name T244
Test name
Test status
Simulation time 231538983 ps
CPU time 2.47 seconds
Started Aug 19 05:24:21 PM PDT 24
Finished Aug 19 05:24:23 PM PDT 24
Peak memory 198248 kb
Host smart-bb34a3f7-7a04-4e09-aedd-7e35edd8de92
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912471646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3912471646
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1872609691
Short name T178
Test name
Test status
Simulation time 1939018067 ps
CPU time 3.5 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:20 PM PDT 24
Peak memory 197316 kb
Host smart-8b022c37-72ee-453b-bbe0-63a15d9b6d56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872609691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1872609691
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4142884659
Short name T313
Test name
Test status
Simulation time 74366409 ps
CPU time 0.7 seconds
Started Aug 19 05:24:16 PM PDT 24
Finished Aug 19 05:24:17 PM PDT 24
Peak memory 194476 kb
Host smart-9a168cce-bb3d-439f-a4a8-531da89408dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142884659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4142884659
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3920730528
Short name T608
Test name
Test status
Simulation time 65795842 ps
CPU time 0.69 seconds
Started Aug 19 05:24:20 PM PDT 24
Finished Aug 19 05:24:21 PM PDT 24
Peak memory 194504 kb
Host smart-5de93e00-0c92-4a34-801c-4efa9aac0da2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920730528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3920730528
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.674317043
Short name T541
Test name
Test status
Simulation time 917563019 ps
CPU time 5.85 seconds
Started Aug 19 05:24:21 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 198204 kb
Host smart-a705f777-b6ab-4ea3-bb47-8dc2e59245ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674317043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.674317043
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2102520650
Short name T110
Test name
Test status
Simulation time 256930034 ps
CPU time 1.24 seconds
Started Aug 19 05:24:17 PM PDT 24
Finished Aug 19 05:24:18 PM PDT 24
Peak memory 195980 kb
Host smart-9235f9f5-04e2-4244-a795-dffe9f235292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102520650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2102520650
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1158372819
Short name T649
Test name
Test status
Simulation time 44943716 ps
CPU time 1.34 seconds
Started Aug 19 05:24:17 PM PDT 24
Finished Aug 19 05:24:18 PM PDT 24
Peak memory 196940 kb
Host smart-ac9dd2ee-39e0-494e-afdc-264eea12e4dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158372819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1158372819
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3683436004
Short name T601
Test name
Test status
Simulation time 56347381870 ps
CPU time 186.36 seconds
Started Aug 19 05:24:18 PM PDT 24
Finished Aug 19 05:27:24 PM PDT 24
Peak memory 198368 kb
Host smart-482fc319-e7ab-4eed-993b-889b03f2d32b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683436004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3683436004
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2805892559
Short name T537
Test name
Test status
Simulation time 11565601155 ps
CPU time 51.43 seconds
Started Aug 19 05:24:29 PM PDT 24
Finished Aug 19 05:25:20 PM PDT 24
Peak memory 198532 kb
Host smart-9a5ed093-5399-4e32-a063-a8aacac1dea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2805892559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2805892559
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.210393649
Short name T195
Test name
Test status
Simulation time 24027846 ps
CPU time 0.59 seconds
Started Aug 19 05:24:25 PM PDT 24
Finished Aug 19 05:24:26 PM PDT 24
Peak memory 195020 kb
Host smart-a9846036-0c64-4f8b-a253-0c4900d942da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210393649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.210393649
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1892240421
Short name T465
Test name
Test status
Simulation time 15448463 ps
CPU time 0.62 seconds
Started Aug 19 05:24:27 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 194084 kb
Host smart-4518e6f3-2c22-4449-a8e9-918a85df72a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892240421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1892240421
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3809563170
Short name T594
Test name
Test status
Simulation time 446452876 ps
CPU time 6.03 seconds
Started Aug 19 05:24:29 PM PDT 24
Finished Aug 19 05:24:35 PM PDT 24
Peak memory 198156 kb
Host smart-53e78af2-f9b8-4d96-8207-1851ef918f0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809563170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3809563170
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3768317952
Short name T544
Test name
Test status
Simulation time 20697846 ps
CPU time 0.62 seconds
Started Aug 19 05:24:27 PM PDT 24
Finished Aug 19 05:24:28 PM PDT 24
Peak memory 194460 kb
Host smart-df4fd026-6483-4c06-bd2f-9476ae4592e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768317952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3768317952
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1996229522
Short name T396
Test name
Test status
Simulation time 48815920 ps
CPU time 1.31 seconds
Started Aug 19 05:24:26 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 197244 kb
Host smart-78f28f92-6aa8-4096-853a-0c8b6f9ac1ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996229522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1996229522
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.4129684427
Short name T628
Test name
Test status
Simulation time 75374167 ps
CPU time 2.94 seconds
Started Aug 19 05:24:28 PM PDT 24
Finished Aug 19 05:24:31 PM PDT 24
Peak memory 198188 kb
Host smart-9680183e-220b-4960-a10c-7256451180f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129684427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.4129684427
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.13001467
Short name T603
Test name
Test status
Simulation time 355368419 ps
CPU time 3.37 seconds
Started Aug 19 05:24:27 PM PDT 24
Finished Aug 19 05:24:30 PM PDT 24
Peak memory 197252 kb
Host smart-497ddac5-dccd-4948-93d7-be3187022533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13001467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.13001467
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1726722873
Short name T433
Test name
Test status
Simulation time 27897715 ps
CPU time 0.88 seconds
Started Aug 19 05:24:24 PM PDT 24
Finished Aug 19 05:24:25 PM PDT 24
Peak memory 197132 kb
Host smart-854ee09f-e806-46d7-994d-06142da0a1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726722873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1726722873
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1471840532
Short name T610
Test name
Test status
Simulation time 154140914 ps
CPU time 1.04 seconds
Started Aug 19 05:24:26 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 196740 kb
Host smart-703ccbb3-ee30-4f19-afa6-7d1c03b011bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471840532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1471840532
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4133659757
Short name T665
Test name
Test status
Simulation time 1021285288 ps
CPU time 6.13 seconds
Started Aug 19 05:24:26 PM PDT 24
Finished Aug 19 05:24:32 PM PDT 24
Peak memory 198084 kb
Host smart-c05a7ac5-aec2-498a-86f8-7bb2cf0fb2c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133659757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4133659757
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2200207903
Short name T190
Test name
Test status
Simulation time 84618361 ps
CPU time 1.4 seconds
Started Aug 19 05:24:25 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 195692 kb
Host smart-d1319707-1be8-4435-8fa1-5ab6f76d80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200207903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2200207903
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2035211472
Short name T348
Test name
Test status
Simulation time 229712802 ps
CPU time 1.19 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:24:43 PM PDT 24
Peak memory 196568 kb
Host smart-5cd67176-47f9-4050-9d04-e6e616cd655d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035211472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2035211472
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2157445837
Short name T191
Test name
Test status
Simulation time 6915807921 ps
CPU time 189.86 seconds
Started Aug 19 05:24:26 PM PDT 24
Finished Aug 19 05:27:36 PM PDT 24
Peak memory 198400 kb
Host smart-0fd86592-1b03-47fc-a87d-47492f32b721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157445837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2157445837
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1313443764
Short name T487
Test name
Test status
Simulation time 17468833 ps
CPU time 0.62 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:24:42 PM PDT 24
Peak memory 194776 kb
Host smart-3120e4ba-0fa8-446d-87df-b3aa40b21d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313443764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1313443764
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.734928427
Short name T429
Test name
Test status
Simulation time 24338600 ps
CPU time 0.86 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:24:43 PM PDT 24
Peak memory 195416 kb
Host smart-6c103c97-857c-448d-8336-279d5854f298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734928427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.734928427
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.17354281
Short name T107
Test name
Test status
Simulation time 1863534128 ps
CPU time 14.93 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:24:57 PM PDT 24
Peak memory 198184 kb
Host smart-62bd793d-002c-4bfd-9b18-9b997380d869
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17354281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stress
.17354281
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2811396502
Short name T2
Test name
Test status
Simulation time 377144443 ps
CPU time 1.01 seconds
Started Aug 19 05:24:27 PM PDT 24
Finished Aug 19 05:24:28 PM PDT 24
Peak memory 196480 kb
Host smart-8ff3465e-0d3a-40cf-9b76-db0f93200911
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811396502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2811396502
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.342764545
Short name T150
Test name
Test status
Simulation time 97191430 ps
CPU time 1.4 seconds
Started Aug 19 05:24:26 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 197184 kb
Host smart-cfd261e5-48be-4eda-880d-2b9f91dda43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342764545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.342764545
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2153736131
Short name T595
Test name
Test status
Simulation time 794245924 ps
CPU time 2.5 seconds
Started Aug 19 05:24:26 PM PDT 24
Finished Aug 19 05:24:29 PM PDT 24
Peak memory 198212 kb
Host smart-daac5731-fe41-42e4-90a6-d860904e997a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153736131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2153736131
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1412638054
Short name T702
Test name
Test status
Simulation time 1120161417 ps
CPU time 2.54 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:24:44 PM PDT 24
Peak memory 198176 kb
Host smart-c49ac7b1-d8f2-4c09-b36e-ce4db5195b94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412638054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1412638054
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3517102320
Short name T496
Test name
Test status
Simulation time 23132360 ps
CPU time 1.01 seconds
Started Aug 19 05:24:27 PM PDT 24
Finished Aug 19 05:24:28 PM PDT 24
Peak memory 196944 kb
Host smart-912b3909-6c0b-4c17-8a9e-94ab55fe7f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517102320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3517102320
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.675348914
Short name T144
Test name
Test status
Simulation time 31902016 ps
CPU time 1.16 seconds
Started Aug 19 05:24:30 PM PDT 24
Finished Aug 19 05:24:31 PM PDT 24
Peak memory 196292 kb
Host smart-ecbc47b2-4654-4815-a9ca-a4e9b8c2767d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675348914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.675348914
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2261644700
Short name T7
Test name
Test status
Simulation time 785383313 ps
CPU time 4.1 seconds
Started Aug 19 05:24:25 PM PDT 24
Finished Aug 19 05:24:29 PM PDT 24
Peak memory 197408 kb
Host smart-7a6efbdd-4e73-4b6c-9450-82229aff9a62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261644700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2261644700
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3974266709
Short name T98
Test name
Test status
Simulation time 81521642 ps
CPU time 1.51 seconds
Started Aug 19 05:24:26 PM PDT 24
Finished Aug 19 05:24:27 PM PDT 24
Peak memory 196476 kb
Host smart-b7e0fa02-f9f5-4c83-b95c-c6126529b9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974266709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3974266709
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2811692084
Short name T430
Test name
Test status
Simulation time 75038230 ps
CPU time 1.13 seconds
Started Aug 19 05:24:27 PM PDT 24
Finished Aug 19 05:24:28 PM PDT 24
Peak memory 195728 kb
Host smart-7347846e-10b0-4083-8b04-f2edefb4507d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811692084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2811692084
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1420013047
Short name T651
Test name
Test status
Simulation time 4066023986 ps
CPU time 28.47 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:25:10 PM PDT 24
Peak memory 198360 kb
Host smart-aef8646e-b05f-443a-81cb-0879551cead4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420013047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1420013047
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2502268437
Short name T577
Test name
Test status
Simulation time 17690473 ps
CPU time 0.53 seconds
Started Aug 19 05:22:36 PM PDT 24
Finished Aug 19 05:22:36 PM PDT 24
Peak memory 192856 kb
Host smart-b39ad015-4883-48f7-a308-63f976e772f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502268437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2502268437
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1802742408
Short name T682
Test name
Test status
Simulation time 43426012 ps
CPU time 0.85 seconds
Started Aug 19 05:22:27 PM PDT 24
Finished Aug 19 05:22:28 PM PDT 24
Peak memory 195604 kb
Host smart-10870d99-1fd4-44d4-9a80-442d012c4065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802742408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1802742408
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1310914001
Short name T678
Test name
Test status
Simulation time 435602217 ps
CPU time 22.05 seconds
Started Aug 19 05:22:27 PM PDT 24
Finished Aug 19 05:22:49 PM PDT 24
Peak memory 196920 kb
Host smart-23414179-34a8-4738-a4b1-25bca49fdfb5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310914001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1310914001
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2527279181
Short name T503
Test name
Test status
Simulation time 872772881 ps
CPU time 0.81 seconds
Started Aug 19 05:22:33 PM PDT 24
Finished Aug 19 05:22:34 PM PDT 24
Peak memory 196332 kb
Host smart-d5b9683c-275e-4b5b-93bb-fe5d5b0f3086
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527279181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2527279181
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1816778501
Short name T479
Test name
Test status
Simulation time 79319890 ps
CPU time 1.41 seconds
Started Aug 19 05:22:24 PM PDT 24
Finished Aug 19 05:22:26 PM PDT 24
Peak memory 198256 kb
Host smart-55757d2c-a1c0-452f-8e78-2e69d490cff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816778501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1816778501
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3124364143
Short name T443
Test name
Test status
Simulation time 224178128 ps
CPU time 2.39 seconds
Started Aug 19 05:22:26 PM PDT 24
Finished Aug 19 05:22:28 PM PDT 24
Peak memory 196440 kb
Host smart-a6c24449-09c1-4cd7-95e0-93e42c2c8012
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124364143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3124364143
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1700165931
Short name T436
Test name
Test status
Simulation time 105931532 ps
CPU time 1.02 seconds
Started Aug 19 05:22:32 PM PDT 24
Finished Aug 19 05:22:33 PM PDT 24
Peak memory 196360 kb
Host smart-a2b86d72-d83a-463d-87aa-50bc0f87f230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700165931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1700165931
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1645130212
Short name T373
Test name
Test status
Simulation time 34514711 ps
CPU time 0.78 seconds
Started Aug 19 05:22:29 PM PDT 24
Finished Aug 19 05:22:30 PM PDT 24
Peak memory 195548 kb
Host smart-9b342637-0da5-49d2-a0fc-512d3581aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645130212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1645130212
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.377032091
Short name T13
Test name
Test status
Simulation time 113445185 ps
CPU time 0.82 seconds
Started Aug 19 05:22:28 PM PDT 24
Finished Aug 19 05:22:29 PM PDT 24
Peak memory 195604 kb
Host smart-7ef08216-9d1d-4788-b0de-6c2accdc8014
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377032091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.377032091
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.787469329
Short name T383
Test name
Test status
Simulation time 94131672 ps
CPU time 4.28 seconds
Started Aug 19 05:22:26 PM PDT 24
Finished Aug 19 05:22:30 PM PDT 24
Peak memory 198108 kb
Host smart-ab138aee-301d-4345-8308-f19b8d8737f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787469329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.787469329
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1529101245
Short name T37
Test name
Test status
Simulation time 363141552 ps
CPU time 0.91 seconds
Started Aug 19 05:22:37 PM PDT 24
Finished Aug 19 05:22:38 PM PDT 24
Peak memory 214036 kb
Host smart-c6d243b1-f5b6-45fd-82d1-aabcf8b96661
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529101245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1529101245
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.8584807
Short name T675
Test name
Test status
Simulation time 36506450 ps
CPU time 1.16 seconds
Started Aug 19 05:22:27 PM PDT 24
Finished Aug 19 05:22:28 PM PDT 24
Peak memory 195692 kb
Host smart-14a16a72-b431-430f-8bc4-32582b2bceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8584807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.8584807
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1587344726
Short name T265
Test name
Test status
Simulation time 328355489 ps
CPU time 1.25 seconds
Started Aug 19 05:22:29 PM PDT 24
Finished Aug 19 05:22:30 PM PDT 24
Peak memory 195712 kb
Host smart-ff508951-c9df-4178-86f8-d32bf85446a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587344726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1587344726
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.831809947
Short name T26
Test name
Test status
Simulation time 30371491262 ps
CPU time 205.49 seconds
Started Aug 19 05:22:33 PM PDT 24
Finished Aug 19 05:25:59 PM PDT 24
Peak memory 198376 kb
Host smart-3f5c38d4-0132-4aa0-b72b-6d04585b2f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831809947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.831809947
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4146789584
Short name T620
Test name
Test status
Simulation time 21980966 ps
CPU time 0.55 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:39 PM PDT 24
Peak memory 194100 kb
Host smart-54a94e8f-dcb2-4f6d-a672-d5113cdd0dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146789584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4146789584
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1594677409
Short name T611
Test name
Test status
Simulation time 26462765 ps
CPU time 0.7 seconds
Started Aug 19 05:24:36 PM PDT 24
Finished Aug 19 05:24:37 PM PDT 24
Peak memory 195408 kb
Host smart-4225c9b0-56bc-465f-9a29-b1a8eba150b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594677409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1594677409
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2717326797
Short name T364
Test name
Test status
Simulation time 636643414 ps
CPU time 7.85 seconds
Started Aug 19 05:24:40 PM PDT 24
Finished Aug 19 05:24:48 PM PDT 24
Peak memory 198120 kb
Host smart-dbfeca54-256f-4f6a-a245-3b3a2c0e6611
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717326797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2717326797
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2285227603
Short name T377
Test name
Test status
Simulation time 96064896 ps
CPU time 0.72 seconds
Started Aug 19 05:24:36 PM PDT 24
Finished Aug 19 05:24:37 PM PDT 24
Peak memory 194924 kb
Host smart-53bc5b40-c263-442f-9558-7e53e7921259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285227603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2285227603
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2669469951
Short name T231
Test name
Test status
Simulation time 178507556 ps
CPU time 0.82 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:39 PM PDT 24
Peak memory 195552 kb
Host smart-fbbc836f-1d3d-441a-8c8c-d382d93bd313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669469951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2669469951
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2235815006
Short name T241
Test name
Test status
Simulation time 58614710 ps
CPU time 2.37 seconds
Started Aug 19 05:24:37 PM PDT 24
Finished Aug 19 05:24:40 PM PDT 24
Peak memory 198256 kb
Host smart-c9fcb228-83cb-406e-ae91-4bc4154d6cdd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235815006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2235815006
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1165849304
Short name T511
Test name
Test status
Simulation time 129033786 ps
CPU time 1.27 seconds
Started Aug 19 05:24:37 PM PDT 24
Finished Aug 19 05:24:39 PM PDT 24
Peak memory 196944 kb
Host smart-2c3e9996-ccb3-447e-8ae9-545d5544b6b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165849304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1165849304
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.959720986
Short name T108
Test name
Test status
Simulation time 92614295 ps
CPU time 1.18 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:39 PM PDT 24
Peak memory 196856 kb
Host smart-3d0d63ce-872e-414d-8f83-5a362117e05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959720986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.959720986
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2312908201
Short name T95
Test name
Test status
Simulation time 114763483 ps
CPU time 1.32 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:40 PM PDT 24
Peak memory 197156 kb
Host smart-76bbe343-5e11-4827-8a3a-53e9493061ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312908201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2312908201
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2707260767
Short name T273
Test name
Test status
Simulation time 126732572 ps
CPU time 5.76 seconds
Started Aug 19 05:24:39 PM PDT 24
Finished Aug 19 05:24:45 PM PDT 24
Peak memory 198220 kb
Host smart-fbaade69-c6cb-4509-aa1c-d37ae32bb7ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707260767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2707260767
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.4033405968
Short name T350
Test name
Test status
Simulation time 220570123 ps
CPU time 1.08 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:24:43 PM PDT 24
Peak memory 195688 kb
Host smart-c8f2a2c6-3b9f-4985-b7e6-b2f3537df595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033405968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.4033405968
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1749916758
Short name T268
Test name
Test status
Simulation time 391033713 ps
CPU time 1.17 seconds
Started Aug 19 05:24:42 PM PDT 24
Finished Aug 19 05:24:43 PM PDT 24
Peak memory 195944 kb
Host smart-55a6015a-41d7-431c-ac57-8c5646a6f116
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749916758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1749916758
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3875832321
Short name T493
Test name
Test status
Simulation time 20403580660 ps
CPU time 206.04 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:28:05 PM PDT 24
Peak memory 198380 kb
Host smart-5474311e-76ae-4d8c-b365-e91b80066c25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875832321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3875832321
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1990371918
Short name T112
Test name
Test status
Simulation time 24100540 ps
CPU time 0.57 seconds
Started Aug 19 05:24:39 PM PDT 24
Finished Aug 19 05:24:40 PM PDT 24
Peak memory 194096 kb
Host smart-ff053368-9834-4c78-8784-7197f0f4314d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990371918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1990371918
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1472140547
Short name T96
Test name
Test status
Simulation time 46355201 ps
CPU time 0.79 seconds
Started Aug 19 05:24:37 PM PDT 24
Finished Aug 19 05:24:38 PM PDT 24
Peak memory 195564 kb
Host smart-8a4fef58-d044-4523-bbfd-5036cf800305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472140547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1472140547
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2976243775
Short name T622
Test name
Test status
Simulation time 542187992 ps
CPU time 15.36 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:54 PM PDT 24
Peak memory 195756 kb
Host smart-a6d63bed-ebff-4a8d-a7f0-aefc91aeed87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976243775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2976243775
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.477500915
Short name T20
Test name
Test status
Simulation time 160037751 ps
CPU time 1.02 seconds
Started Aug 19 05:24:37 PM PDT 24
Finished Aug 19 05:24:39 PM PDT 24
Peak memory 196692 kb
Host smart-ae633d74-80f3-40be-ae76-05cb786d748e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477500915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.477500915
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4185818476
Short name T303
Test name
Test status
Simulation time 82340107 ps
CPU time 0.96 seconds
Started Aug 19 05:24:40 PM PDT 24
Finished Aug 19 05:24:41 PM PDT 24
Peak memory 197568 kb
Host smart-5d12dafe-1221-448a-9a85-369b4c6627a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185818476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4185818476
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2907794596
Short name T472
Test name
Test status
Simulation time 99714329 ps
CPU time 3.82 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:42 PM PDT 24
Peak memory 198252 kb
Host smart-87e6fcd8-523b-4340-9788-749444fb44ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907794596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2907794596
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.809863980
Short name T490
Test name
Test status
Simulation time 395818134 ps
CPU time 2.01 seconds
Started Aug 19 05:24:40 PM PDT 24
Finished Aug 19 05:24:42 PM PDT 24
Peak memory 195920 kb
Host smart-67f1e5c3-79bf-4ed6-bf91-966022bdc5ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809863980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
809863980
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3896620144
Short name T203
Test name
Test status
Simulation time 92774916 ps
CPU time 0.72 seconds
Started Aug 19 05:24:39 PM PDT 24
Finished Aug 19 05:24:40 PM PDT 24
Peak memory 195508 kb
Host smart-1ffc57fd-13ee-49c7-9751-04ed7eed25c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896620144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3896620144
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.844295836
Short name T466
Test name
Test status
Simulation time 213223211 ps
CPU time 1.19 seconds
Started Aug 19 05:24:39 PM PDT 24
Finished Aug 19 05:24:41 PM PDT 24
Peak memory 196104 kb
Host smart-c3c17099-5ee5-412a-b5c0-4ef221133bdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844295836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.844295836
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2078259659
Short name T460
Test name
Test status
Simulation time 2076719213 ps
CPU time 6.73 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:44 PM PDT 24
Peak memory 198120 kb
Host smart-0d6be40d-a57c-4a3b-ae5b-955fd2efedfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078259659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2078259659
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3541225705
Short name T52
Test name
Test status
Simulation time 76481825 ps
CPU time 1.43 seconds
Started Aug 19 05:24:39 PM PDT 24
Finished Aug 19 05:24:41 PM PDT 24
Peak memory 197012 kb
Host smart-aae3a081-82a6-4e70-a02b-b54b3a5f2136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541225705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3541225705
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4242054996
Short name T677
Test name
Test status
Simulation time 28808114 ps
CPU time 0.78 seconds
Started Aug 19 05:24:35 PM PDT 24
Finished Aug 19 05:24:36 PM PDT 24
Peak memory 196004 kb
Host smart-72844335-b0b2-493b-a9e9-e1ba44195c42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242054996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4242054996
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2604310727
Short name T10
Test name
Test status
Simulation time 14743308212 ps
CPU time 190.92 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:27:49 PM PDT 24
Peak memory 198336 kb
Host smart-d5d8d47e-0b4b-4de9-95ed-74f4fa33c13a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604310727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2604310727
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.596895387
Short name T133
Test name
Test status
Simulation time 16628756 ps
CPU time 0.6 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:24:50 PM PDT 24
Peak memory 194240 kb
Host smart-424df70e-cf3b-4f97-a125-0d50d84b6b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596895387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.596895387
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2772455220
Short name T376
Test name
Test status
Simulation time 35064881 ps
CPU time 0.65 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:39 PM PDT 24
Peak memory 194236 kb
Host smart-2bee6ebd-dcc8-4f68-bf3a-076921cd3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772455220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2772455220
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4103167386
Short name T708
Test name
Test status
Simulation time 406062934 ps
CPU time 10.06 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:48 PM PDT 24
Peak memory 196976 kb
Host smart-bf2cd583-bedd-4f4a-89f4-35790e73c632
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103167386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4103167386
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3643545115
Short name T245
Test name
Test status
Simulation time 107950453 ps
CPU time 1.1 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 196792 kb
Host smart-7d71deaa-d59e-4876-b98f-f4a001e967fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643545115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3643545115
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.29386503
Short name T311
Test name
Test status
Simulation time 35455749 ps
CPU time 0.8 seconds
Started Aug 19 05:24:36 PM PDT 24
Finished Aug 19 05:24:37 PM PDT 24
Peak memory 195700 kb
Host smart-dc7c4b9f-dd91-4fe4-b806-3b72191ac1a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29386503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.29386503
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.378766814
Short name T252
Test name
Test status
Simulation time 57374929 ps
CPU time 2.39 seconds
Started Aug 19 05:24:39 PM PDT 24
Finished Aug 19 05:24:42 PM PDT 24
Peak memory 198220 kb
Host smart-92375a84-f1cc-4909-92e4-2d95307b481c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378766814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.378766814
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.941830222
Short name T510
Test name
Test status
Simulation time 67915640 ps
CPU time 2.05 seconds
Started Aug 19 05:24:39 PM PDT 24
Finished Aug 19 05:24:41 PM PDT 24
Peak memory 197272 kb
Host smart-a3512eb8-90d6-4c9b-895b-53b0f8124ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941830222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
941830222
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1472574716
Short name T468
Test name
Test status
Simulation time 59435443 ps
CPU time 1.01 seconds
Started Aug 19 05:24:37 PM PDT 24
Finished Aug 19 05:24:38 PM PDT 24
Peak memory 196144 kb
Host smart-4e49a82a-4211-4b34-82e8-09a3a0aca499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472574716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1472574716
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.404374688
Short name T501
Test name
Test status
Simulation time 128058238 ps
CPU time 1.16 seconds
Started Aug 19 05:24:36 PM PDT 24
Finished Aug 19 05:24:37 PM PDT 24
Peak memory 196748 kb
Host smart-ed13d096-413e-48d3-a15f-9b4cabc11105
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404374688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.404374688
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2023381201
Short name T267
Test name
Test status
Simulation time 490313706 ps
CPU time 3.07 seconds
Started Aug 19 05:24:53 PM PDT 24
Finished Aug 19 05:24:56 PM PDT 24
Peak memory 198176 kb
Host smart-a3ad6443-781d-44a9-a740-93d1ecfbbe95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023381201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2023381201
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2547003479
Short name T180
Test name
Test status
Simulation time 32195205 ps
CPU time 0.94 seconds
Started Aug 19 05:24:38 PM PDT 24
Finished Aug 19 05:24:40 PM PDT 24
Peak memory 195568 kb
Host smart-b1cb5bb1-7137-4dc0-a2de-bedb6502b039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547003479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2547003479
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1661701910
Short name T713
Test name
Test status
Simulation time 332169035 ps
CPU time 1.17 seconds
Started Aug 19 05:24:37 PM PDT 24
Finished Aug 19 05:24:39 PM PDT 24
Peak memory 196468 kb
Host smart-552bd1df-cf83-43fc-9899-85581be0e44b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661701910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1661701910
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3585289370
Short name T384
Test name
Test status
Simulation time 41742391650 ps
CPU time 106.5 seconds
Started Aug 19 05:24:53 PM PDT 24
Finished Aug 19 05:26:39 PM PDT 24
Peak memory 198380 kb
Host smart-4e11f6a3-dcb2-4ed4-8f14-ebe32fb30836
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585289370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3585289370
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.526397813
Short name T523
Test name
Test status
Simulation time 13985598 ps
CPU time 0.59 seconds
Started Aug 19 05:24:53 PM PDT 24
Finished Aug 19 05:24:53 PM PDT 24
Peak memory 194088 kb
Host smart-aa6056f1-e05b-457b-b73d-5b6ca694b03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526397813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.526397813
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.4226051730
Short name T51
Test name
Test status
Simulation time 35600314 ps
CPU time 0.81 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 196180 kb
Host smart-90641f32-6ae2-40e7-80f3-8996aaf6db03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226051730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.4226051730
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.402569311
Short name T647
Test name
Test status
Simulation time 482986279 ps
CPU time 12.7 seconds
Started Aug 19 05:24:51 PM PDT 24
Finished Aug 19 05:25:04 PM PDT 24
Peak memory 196972 kb
Host smart-73ba63ba-0980-452a-b6af-fa469268f09d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402569311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.402569311
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1969503571
Short name T499
Test name
Test status
Simulation time 600817054 ps
CPU time 0.99 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:24:49 PM PDT 24
Peak memory 196860 kb
Host smart-c42a553a-a8e5-4321-aefe-35c3ed1cc412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969503571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1969503571
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2976236799
Short name T659
Test name
Test status
Simulation time 168395681 ps
CPU time 1.25 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:52 PM PDT 24
Peak memory 196256 kb
Host smart-a40ee498-39a0-42db-9c76-a8c8f629297f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976236799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2976236799
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2865110799
Short name T25
Test name
Test status
Simulation time 74453842 ps
CPU time 1.73 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 198300 kb
Host smart-782ebfdc-9d8b-4473-9a94-8e8a12b16321
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865110799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2865110799
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1187570742
Short name T118
Test name
Test status
Simulation time 657906825 ps
CPU time 2.51 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 197364 kb
Host smart-95eb727d-89df-447c-9682-e2c82ad67991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187570742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1187570742
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3839888443
Short name T369
Test name
Test status
Simulation time 90959431 ps
CPU time 0.99 seconds
Started Aug 19 05:24:51 PM PDT 24
Finished Aug 19 05:24:52 PM PDT 24
Peak memory 196124 kb
Host smart-f306406d-58ee-4391-83c9-bae82602a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839888443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3839888443
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3124970822
Short name T155
Test name
Test status
Simulation time 74826660 ps
CPU time 0.71 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:24:49 PM PDT 24
Peak memory 196168 kb
Host smart-88d0e65a-bc71-4c55-be37-f4782c20dfe8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124970822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3124970822
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2224634537
Short name T570
Test name
Test status
Simulation time 1483581050 ps
CPU time 3.08 seconds
Started Aug 19 05:24:51 PM PDT 24
Finished Aug 19 05:24:54 PM PDT 24
Peak memory 198140 kb
Host smart-5d2fc3bf-00bd-4e94-8930-cf525c704fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224634537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2224634537
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3000885727
Short name T331
Test name
Test status
Simulation time 126454401 ps
CPU time 1.32 seconds
Started Aug 19 05:24:46 PM PDT 24
Finished Aug 19 05:24:48 PM PDT 24
Peak memory 198140 kb
Host smart-8d7cf721-13ce-4097-a862-0703b38fa471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000885727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3000885727
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2085771033
Short name T97
Test name
Test status
Simulation time 28045729 ps
CPU time 0.89 seconds
Started Aug 19 05:24:53 PM PDT 24
Finished Aug 19 05:24:54 PM PDT 24
Peak memory 195532 kb
Host smart-ffa705d4-2de2-4aa4-88b8-58cd5e5d2e8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085771033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2085771033
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1875734718
Short name T196
Test name
Test status
Simulation time 15000789997 ps
CPU time 183.44 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:27:53 PM PDT 24
Peak memory 198352 kb
Host smart-f76e0421-46a5-457b-b8fb-65750d520436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875734718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1875734718
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3742262629
Short name T281
Test name
Test status
Simulation time 18649355 ps
CPU time 0.56 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 194268 kb
Host smart-835ad537-8c67-419e-8792-b0753c6b2e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742262629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3742262629
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1440199714
Short name T475
Test name
Test status
Simulation time 232469124 ps
CPU time 0.79 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 195544 kb
Host smart-ee2fb0cc-88ff-44d0-8ce6-9078b5453234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440199714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1440199714
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4058549593
Short name T495
Test name
Test status
Simulation time 1659359348 ps
CPU time 27.51 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 198208 kb
Host smart-1066fdf8-3bad-4010-bb0c-33985f1519fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058549593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4058549593
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.590682825
Short name T435
Test name
Test status
Simulation time 50400542 ps
CPU time 0.87 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:24:59 PM PDT 24
Peak memory 197408 kb
Host smart-ce0730e9-95d4-43d1-810b-b6972a8043dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590682825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.590682825
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1233155425
Short name T539
Test name
Test status
Simulation time 132951707 ps
CPU time 0.88 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 195800 kb
Host smart-392058ac-e9a4-40b1-8c86-890cd4219360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233155425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1233155425
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4285825216
Short name T188
Test name
Test status
Simulation time 37153645 ps
CPU time 1.35 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:24:50 PM PDT 24
Peak memory 198152 kb
Host smart-c6416e8d-bd17-4bd1-9d25-d0c9e7597762
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285825216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4285825216
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3065985189
Short name T660
Test name
Test status
Simulation time 65533524 ps
CPU time 1.63 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 195976 kb
Host smart-ae58f9d6-d172-46dd-9da9-97c270f13100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065985189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3065985189
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1692509400
Short name T715
Test name
Test status
Simulation time 53393864 ps
CPU time 1.19 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 196008 kb
Host smart-5aa798aa-dc68-47ac-b723-d9f71ae24984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692509400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1692509400
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4006675815
Short name T16
Test name
Test status
Simulation time 107265643 ps
CPU time 1.12 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 196180 kb
Host smart-2043cbe4-8e41-4526-9fc1-c737eacffadb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006675815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4006675815
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_smoke.2253610801
Short name T127
Test name
Test status
Simulation time 638826700 ps
CPU time 1.41 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 196932 kb
Host smart-0ae98755-55a3-4bdc-9240-3b59c7d2c6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253610801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2253610801
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2444622310
Short name T452
Test name
Test status
Simulation time 121845645 ps
CPU time 1.23 seconds
Started Aug 19 05:24:47 PM PDT 24
Finished Aug 19 05:24:48 PM PDT 24
Peak memory 196732 kb
Host smart-a9def558-a2b0-4730-a4b1-9967fa92360b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444622310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2444622310
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1236193860
Short name T9
Test name
Test status
Simulation time 1127098621 ps
CPU time 12.87 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:25:01 PM PDT 24
Peak memory 198216 kb
Host smart-1a663484-ad88-43e0-85dd-c4a5d10e2fc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236193860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1236193860
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.874899917
Short name T527
Test name
Test status
Simulation time 11662194 ps
CPU time 0.58 seconds
Started Aug 19 05:24:53 PM PDT 24
Finished Aug 19 05:24:54 PM PDT 24
Peak memory 194068 kb
Host smart-a8ebec3a-b735-40b8-b035-35a29227d0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874899917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.874899917
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2044416611
Short name T710
Test name
Test status
Simulation time 150809908 ps
CPU time 0.87 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:24:50 PM PDT 24
Peak memory 195508 kb
Host smart-f13c2cc7-c391-44dd-bd92-cb24920904d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044416611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2044416611
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1071930173
Short name T504
Test name
Test status
Simulation time 688502158 ps
CPU time 19.89 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:25:09 PM PDT 24
Peak memory 195696 kb
Host smart-7058d33c-b7c2-4d25-9c09-7fe743926f74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071930173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1071930173
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3706194526
Short name T128
Test name
Test status
Simulation time 193898491 ps
CPU time 0.75 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 196672 kb
Host smart-3808f88f-95f3-45b5-8061-98fa62712829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706194526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3706194526
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.759722034
Short name T119
Test name
Test status
Simulation time 24186833 ps
CPU time 0.76 seconds
Started Aug 19 05:24:47 PM PDT 24
Finished Aug 19 05:24:48 PM PDT 24
Peak memory 195284 kb
Host smart-e45f1c29-5654-4d7a-b986-55a5eccdcb33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759722034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.759722034
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.936470044
Short name T536
Test name
Test status
Simulation time 32596015 ps
CPU time 1.12 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:24:49 PM PDT 24
Peak memory 196416 kb
Host smart-8b2c2ff5-cb41-44f6-b50e-9a13665dec3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936470044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.936470044
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1230464318
Short name T389
Test name
Test status
Simulation time 428319201 ps
CPU time 3.1 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:24:52 PM PDT 24
Peak memory 197176 kb
Host smart-d121b513-6066-4b11-b9b2-62c9c26e52d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230464318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1230464318
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3138434967
Short name T633
Test name
Test status
Simulation time 99032064 ps
CPU time 0.81 seconds
Started Aug 19 05:24:53 PM PDT 24
Finished Aug 19 05:24:54 PM PDT 24
Peak memory 195608 kb
Host smart-baee4919-ef75-4f5d-b5a0-0aa87e428238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138434967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3138434967
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3504811438
Short name T321
Test name
Test status
Simulation time 48958094 ps
CPU time 1.04 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:51 PM PDT 24
Peak memory 196104 kb
Host smart-3c59380b-b4cf-47e5-b9cd-7bfdc60b0b08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504811438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3504811438
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1921154886
Short name T298
Test name
Test status
Simulation time 157526562 ps
CPU time 1.41 seconds
Started Aug 19 05:24:51 PM PDT 24
Finished Aug 19 05:24:53 PM PDT 24
Peak memory 198024 kb
Host smart-4691ceb7-7435-4f0a-96c4-ab9398fdef58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921154886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1921154886
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.111680502
Short name T307
Test name
Test status
Simulation time 83117519 ps
CPU time 1.3 seconds
Started Aug 19 05:24:47 PM PDT 24
Finished Aug 19 05:24:48 PM PDT 24
Peak memory 196088 kb
Host smart-e8bcf972-caec-4680-b687-3e1c6970b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111680502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.111680502
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1985262586
Short name T334
Test name
Test status
Simulation time 125595680 ps
CPU time 1.2 seconds
Started Aug 19 05:24:49 PM PDT 24
Finished Aug 19 05:24:50 PM PDT 24
Peak memory 195820 kb
Host smart-9a4d8b72-91bb-422f-bcef-a413415ccbcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985262586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1985262586
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3776279330
Short name T554
Test name
Test status
Simulation time 27241895548 ps
CPU time 51.69 seconds
Started Aug 19 05:24:48 PM PDT 24
Finished Aug 19 05:25:40 PM PDT 24
Peak memory 198332 kb
Host smart-1ffdf8a0-da75-42d6-b15f-07c01ed60fc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776279330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3776279330
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2466016127
Short name T236
Test name
Test status
Simulation time 22231398171 ps
CPU time 167.4 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:27:45 PM PDT 24
Peak memory 198584 kb
Host smart-6485aad1-ed58-46e3-a3cf-15371dd05678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2466016127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2466016127
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2938735047
Short name T182
Test name
Test status
Simulation time 15470631 ps
CPU time 0.57 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 194804 kb
Host smart-cf98d097-a2c5-4d59-b04a-88c81a6c4682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938735047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2938735047
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.612092757
Short name T200
Test name
Test status
Simulation time 36359489 ps
CPU time 0.9 seconds
Started Aug 19 05:24:55 PM PDT 24
Finished Aug 19 05:24:56 PM PDT 24
Peak memory 196368 kb
Host smart-c67ccb60-7542-4830-a246-76b0cb5cf5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612092757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.612092757
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3508045298
Short name T632
Test name
Test status
Simulation time 3555844667 ps
CPU time 25.81 seconds
Started Aug 19 05:25:01 PM PDT 24
Finished Aug 19 05:25:27 PM PDT 24
Peak memory 197152 kb
Host smart-29b4fab5-480f-4fc3-b3f7-23ea825c0832
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508045298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3508045298
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.429327244
Short name T711
Test name
Test status
Simulation time 28071805 ps
CPU time 0.72 seconds
Started Aug 19 05:24:59 PM PDT 24
Finished Aug 19 05:25:00 PM PDT 24
Peak memory 195464 kb
Host smart-7e7d8cde-520b-43c0-b4d5-35d1a9f0c6ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429327244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.429327244
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.4187616595
Short name T275
Test name
Test status
Simulation time 85811733 ps
CPU time 0.71 seconds
Started Aug 19 05:25:01 PM PDT 24
Finished Aug 19 05:25:02 PM PDT 24
Peak memory 194452 kb
Host smart-0aab768d-8911-400f-b8bf-1683a8a2a77b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187616595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.4187616595
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3255537579
Short name T456
Test name
Test status
Simulation time 52690617 ps
CPU time 2.11 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:24:59 PM PDT 24
Peak memory 198216 kb
Host smart-ca8d954e-7a73-4efc-9d31-ae30d7c9e324
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255537579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3255537579
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.345800870
Short name T202
Test name
Test status
Simulation time 135394460 ps
CPU time 2.24 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 197148 kb
Host smart-15b21d83-6850-4faa-a0f7-b365422351fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345800870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
345800870
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3837625660
Short name T645
Test name
Test status
Simulation time 44751721 ps
CPU time 0.73 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:24:59 PM PDT 24
Peak memory 195488 kb
Host smart-19e299c9-ea67-4fb0-8570-0239b9a44fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837625660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3837625660
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.517699584
Short name T270
Test name
Test status
Simulation time 40682950 ps
CPU time 0.9 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:24:57 PM PDT 24
Peak memory 196056 kb
Host smart-08bbfba7-32c4-44c0-b671-f6a7f329ea95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517699584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.517699584
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2841778270
Short name T228
Test name
Test status
Simulation time 107296608 ps
CPU time 5.22 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:25:03 PM PDT 24
Peak memory 198156 kb
Host smart-a79e284b-79fb-4e62-9314-64c2971bcea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841778270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2841778270
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4156843334
Short name T19
Test name
Test status
Simulation time 88819568 ps
CPU time 1.31 seconds
Started Aug 19 05:24:50 PM PDT 24
Finished Aug 19 05:24:52 PM PDT 24
Peak memory 197068 kb
Host smart-0d0d2569-7b21-49f1-b7f1-77a791624d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156843334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4156843334
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1478787763
Short name T111
Test name
Test status
Simulation time 231065396 ps
CPU time 1.31 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 196600 kb
Host smart-eed99161-4cd9-4dfe-8e16-67d846128d65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478787763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1478787763
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.992670868
Short name T684
Test name
Test status
Simulation time 27840386762 ps
CPU time 167 seconds
Started Aug 19 05:24:59 PM PDT 24
Finished Aug 19 05:27:46 PM PDT 24
Peak memory 198340 kb
Host smart-142f5e7c-bf2c-4b42-9b4f-2b6b6f8a3c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992670868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.992670868
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3948600285
Short name T40
Test name
Test status
Simulation time 16930634 ps
CPU time 0.57 seconds
Started Aug 19 05:25:00 PM PDT 24
Finished Aug 19 05:25:00 PM PDT 24
Peak memory 194996 kb
Host smart-c0cfdcff-9ffb-4696-80bc-c6da99d2cd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948600285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3948600285
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2099451946
Short name T491
Test name
Test status
Simulation time 22603576 ps
CPU time 0.67 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:24:59 PM PDT 24
Peak memory 194156 kb
Host smart-fa62b4de-ae83-4d33-8cca-f707c2b4e9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099451946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2099451946
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.899923671
Short name T277
Test name
Test status
Simulation time 491609719 ps
CPU time 26.12 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:25:22 PM PDT 24
Peak memory 197104 kb
Host smart-bc0e10d8-9106-4717-a3be-a76e7b552fd8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899923671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.899923671
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.529249048
Short name T540
Test name
Test status
Simulation time 404596977 ps
CPU time 1.03 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 196744 kb
Host smart-558b873c-1e49-4bb2-9c21-4a20772e52bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529249048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.529249048
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3384843351
Short name T453
Test name
Test status
Simulation time 1037601432 ps
CPU time 1.28 seconds
Started Aug 19 05:25:00 PM PDT 24
Finished Aug 19 05:25:01 PM PDT 24
Peak memory 196228 kb
Host smart-e8c40267-bf30-48f4-8435-58bf9cb9c34c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384843351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3384843351
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1401608707
Short name T91
Test name
Test status
Simulation time 63807109 ps
CPU time 2.61 seconds
Started Aug 19 05:24:59 PM PDT 24
Finished Aug 19 05:25:02 PM PDT 24
Peak memory 198272 kb
Host smart-cd1b98ff-81ca-4c90-b8de-0ac233a7ce67
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401608707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1401608707
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1661870759
Short name T93
Test name
Test status
Simulation time 127679278 ps
CPU time 2.91 seconds
Started Aug 19 05:25:02 PM PDT 24
Finished Aug 19 05:25:05 PM PDT 24
Peak memory 197488 kb
Host smart-519d2f22-b5db-4adb-9ae9-8ff83889d35d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661870759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1661870759
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1926502181
Short name T222
Test name
Test status
Simulation time 45060013 ps
CPU time 0.77 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 195652 kb
Host smart-15d9b389-0bda-4935-8acf-c05cdbc1005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926502181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1926502181
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2354369458
Short name T629
Test name
Test status
Simulation time 74146996 ps
CPU time 1.38 seconds
Started Aug 19 05:25:00 PM PDT 24
Finished Aug 19 05:25:02 PM PDT 24
Peak memory 197080 kb
Host smart-aaa5c5bc-d5aa-4c0c-8f53-c4dbf12dc468
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354369458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2354369458
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3133840756
Short name T262
Test name
Test status
Simulation time 103149782 ps
CPU time 4.08 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:25:02 PM PDT 24
Peak memory 198144 kb
Host smart-731c966b-61b2-48d5-9d50-f01b6f0a0a29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133840756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3133840756
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3130972791
Short name T106
Test name
Test status
Simulation time 578407267 ps
CPU time 1.25 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:24:59 PM PDT 24
Peak memory 196036 kb
Host smart-9e781805-6926-4da8-9f15-832e81ed6f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130972791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3130972791
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3701527796
Short name T535
Test name
Test status
Simulation time 197610109 ps
CPU time 0.85 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:24:57 PM PDT 24
Peak memory 195416 kb
Host smart-42895085-2eff-499f-af7d-7b5fa7610f45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701527796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3701527796
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.223884614
Short name T652
Test name
Test status
Simulation time 20314900804 ps
CPU time 222.76 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:28:40 PM PDT 24
Peak memory 198380 kb
Host smart-af4bb36e-e938-4247-a796-c59ff0c94ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223884614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.223884614
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2711987254
Short name T669
Test name
Test status
Simulation time 13424010 ps
CPU time 0.58 seconds
Started Aug 19 05:25:04 PM PDT 24
Finished Aug 19 05:25:05 PM PDT 24
Peak memory 193916 kb
Host smart-d18f438d-5e2a-41f0-a46c-20229a95970d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711987254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2711987254
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1242076087
Short name T498
Test name
Test status
Simulation time 51011888 ps
CPU time 0.97 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:24:57 PM PDT 24
Peak memory 197448 kb
Host smart-aa44087d-4520-468a-adec-e04c2f933763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242076087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1242076087
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.4035677363
Short name T516
Test name
Test status
Simulation time 1674003395 ps
CPU time 21.96 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 197144 kb
Host smart-bd63908d-0724-4b47-968c-637dfe9e92f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035677363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.4035677363
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.577283580
Short name T533
Test name
Test status
Simulation time 502102078 ps
CPU time 0.93 seconds
Started Aug 19 05:24:56 PM PDT 24
Finished Aug 19 05:24:57 PM PDT 24
Peak memory 198012 kb
Host smart-d520388a-3991-4f3b-9bbd-705b42ec6a8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577283580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.577283580
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3866734333
Short name T322
Test name
Test status
Simulation time 76752080 ps
CPU time 1.26 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 196320 kb
Host smart-385311ce-0eca-409e-b10e-d9634b970ccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866734333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3866734333
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2547850371
Short name T134
Test name
Test status
Simulation time 50972714 ps
CPU time 2.33 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:25:00 PM PDT 24
Peak memory 198204 kb
Host smart-e0423ad9-0ac1-476d-9341-1a818a52cd06
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547850371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2547850371
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2380220796
Short name T447
Test name
Test status
Simulation time 157041678 ps
CPU time 3.38 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:25:01 PM PDT 24
Peak memory 196012 kb
Host smart-1ad6c9bf-1a05-401f-8e22-6dc80a6e2988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380220796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2380220796
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.604773175
Short name T166
Test name
Test status
Simulation time 22982649 ps
CPU time 0.64 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 194440 kb
Host smart-09c518f1-9a78-4d05-bc64-e3fb6e21170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604773175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.604773175
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3942939571
Short name T220
Test name
Test status
Simulation time 101405880 ps
CPU time 0.82 seconds
Started Aug 19 05:24:58 PM PDT 24
Finished Aug 19 05:24:59 PM PDT 24
Peak memory 195616 kb
Host smart-84b791cd-50f7-433e-a713-ea23eefcba07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942939571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3942939571
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.269082780
Short name T206
Test name
Test status
Simulation time 81658769 ps
CPU time 1.56 seconds
Started Aug 19 05:25:00 PM PDT 24
Finished Aug 19 05:25:01 PM PDT 24
Peak memory 198156 kb
Host smart-b63c080b-97d8-414e-a692-674a4d5928d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269082780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.269082780
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2537422448
Short name T676
Test name
Test status
Simulation time 82583265 ps
CPU time 1.03 seconds
Started Aug 19 05:25:02 PM PDT 24
Finished Aug 19 05:25:03 PM PDT 24
Peak memory 196688 kb
Host smart-965a9108-24dd-4885-bda9-6ef2d1ab8d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537422448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2537422448
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3548336327
Short name T613
Test name
Test status
Simulation time 25093338 ps
CPU time 0.8 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:24:58 PM PDT 24
Peak memory 195476 kb
Host smart-5165f2a8-4b93-4909-b075-7a89de9531ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548336327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3548336327
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3533578083
Short name T604
Test name
Test status
Simulation time 22344715052 ps
CPU time 40.83 seconds
Started Aug 19 05:24:57 PM PDT 24
Finished Aug 19 05:25:38 PM PDT 24
Peak memory 198352 kb
Host smart-59efd7ac-854c-4e31-9fd1-677ea86ad165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533578083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3533578083
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1665092753
Short name T139
Test name
Test status
Simulation time 20155165 ps
CPU time 0.58 seconds
Started Aug 19 05:25:05 PM PDT 24
Finished Aug 19 05:25:06 PM PDT 24
Peak memory 194068 kb
Host smart-8a8064fe-d934-4e80-90c3-be7204fdbc51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665092753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1665092753
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.4251776229
Short name T488
Test name
Test status
Simulation time 83380046 ps
CPU time 0.75 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 195432 kb
Host smart-a92f98d1-f75c-430e-880b-a11857433842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251776229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.4251776229
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.675083679
Short name T393
Test name
Test status
Simulation time 406651464 ps
CPU time 11.01 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:19 PM PDT 24
Peak memory 195724 kb
Host smart-bc38ca40-278f-418b-908d-c99e06ebe444
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675083679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.675083679
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.125005370
Short name T483
Test name
Test status
Simulation time 272003912 ps
CPU time 1.04 seconds
Started Aug 19 05:25:10 PM PDT 24
Finished Aug 19 05:25:11 PM PDT 24
Peak memory 198020 kb
Host smart-6ef59f3c-e466-485b-84c3-8e10e060534e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125005370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.125005370
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.665892539
Short name T318
Test name
Test status
Simulation time 136487376 ps
CPU time 1.01 seconds
Started Aug 19 05:25:05 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 196136 kb
Host smart-a47f25b4-a449-460e-9825-bca605142dbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665892539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.665892539
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.448146509
Short name T380
Test name
Test status
Simulation time 171739317 ps
CPU time 3.78 seconds
Started Aug 19 05:25:05 PM PDT 24
Finished Aug 19 05:25:09 PM PDT 24
Peak memory 198184 kb
Host smart-3c919bbc-5689-4600-a148-d4ca58cf39aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448146509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.448146509
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3614506113
Short name T103
Test name
Test status
Simulation time 156422148 ps
CPU time 1.22 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 195812 kb
Host smart-8bd2bd10-4fba-401e-b2ba-cded95d409cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614506113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3614506113
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1007052473
Short name T264
Test name
Test status
Simulation time 98637897 ps
CPU time 1.03 seconds
Started Aug 19 05:25:05 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 196116 kb
Host smart-0ddf1a36-fc68-4c1c-930b-a2b917fdbf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007052473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1007052473
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2256448992
Short name T438
Test name
Test status
Simulation time 14906107 ps
CPU time 0.7 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 194428 kb
Host smart-45e2fe10-1f5d-4d07-9aaa-fabebfe4b6b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256448992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2256448992
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1052498784
Short name T464
Test name
Test status
Simulation time 1611461127 ps
CPU time 3.85 seconds
Started Aug 19 05:25:07 PM PDT 24
Finished Aug 19 05:25:11 PM PDT 24
Peak memory 198200 kb
Host smart-3db0f43a-43be-4a31-89e3-f47fede5525c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052498784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1052498784
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.809216630
Short name T374
Test name
Test status
Simulation time 83967402 ps
CPU time 1.26 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:09 PM PDT 24
Peak memory 196460 kb
Host smart-bc4b96d2-2f1f-4c07-ad27-afe5e33cab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809216630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.809216630
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1969219800
Short name T141
Test name
Test status
Simulation time 38259560 ps
CPU time 1.18 seconds
Started Aug 19 05:25:13 PM PDT 24
Finished Aug 19 05:25:14 PM PDT 24
Peak memory 195888 kb
Host smart-c233446b-823b-4151-951f-34498e2ba4ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969219800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1969219800
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1116173547
Short name T153
Test name
Test status
Simulation time 23031699121 ps
CPU time 137.02 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:27:25 PM PDT 24
Peak memory 198376 kb
Host smart-54267a33-29b4-4b6d-8702-91fefab8f2e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116173547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1116173547
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3924301534
Short name T41
Test name
Test status
Simulation time 11887001 ps
CPU time 0.57 seconds
Started Aug 19 05:22:45 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 194808 kb
Host smart-c2b5a4db-ec7a-4db8-aff9-69a7b07538b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924301534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3924301534
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4138019569
Short name T257
Test name
Test status
Simulation time 87867157 ps
CPU time 0.8 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 196328 kb
Host smart-39ccf4d2-5155-4e5a-995e-0a70548fd556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138019569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4138019569
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.4260647415
Short name T515
Test name
Test status
Simulation time 1257730853 ps
CPU time 17.33 seconds
Started Aug 19 05:22:34 PM PDT 24
Finished Aug 19 05:22:51 PM PDT 24
Peak memory 197056 kb
Host smart-227034c4-70a1-4415-9ac4-dd84625ce86b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260647415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.4260647415
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3236006485
Short name T23
Test name
Test status
Simulation time 194008690 ps
CPU time 1.02 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 196812 kb
Host smart-c27b4173-2bc2-4c02-b385-cd66b1a330e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236006485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3236006485
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2473524449
Short name T526
Test name
Test status
Simulation time 35158838 ps
CPU time 0.97 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 196208 kb
Host smart-b7c94e91-537e-4984-b60f-1f4a4e9a43c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473524449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2473524449
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3089177961
Short name T418
Test name
Test status
Simulation time 27525102 ps
CPU time 1.33 seconds
Started Aug 19 05:22:35 PM PDT 24
Finished Aug 19 05:22:36 PM PDT 24
Peak memory 198280 kb
Host smart-f8e03629-b606-460b-82c3-7b7b96ff7b4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089177961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3089177961
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.27895620
Short name T497
Test name
Test status
Simulation time 148253666 ps
CPU time 2.98 seconds
Started Aug 19 05:22:33 PM PDT 24
Finished Aug 19 05:22:37 PM PDT 24
Peak memory 197136 kb
Host smart-ea7ccab7-9ad1-4c10-aab4-f171618f0e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27895620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.27895620
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3924591299
Short name T486
Test name
Test status
Simulation time 207553050 ps
CPU time 1.02 seconds
Started Aug 19 05:22:35 PM PDT 24
Finished Aug 19 05:22:36 PM PDT 24
Peak memory 196176 kb
Host smart-07f5a5e9-403d-49a4-a3b2-0713f0833d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924591299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3924591299
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1830679239
Short name T648
Test name
Test status
Simulation time 547906662 ps
CPU time 1.27 seconds
Started Aug 19 05:22:34 PM PDT 24
Finished Aug 19 05:22:35 PM PDT 24
Peak memory 196752 kb
Host smart-cd40ab42-83dc-46e3-97b1-0175899adda8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830679239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1830679239
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.156054416
Short name T312
Test name
Test status
Simulation time 228430063 ps
CPU time 2.34 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 198164 kb
Host smart-820f95e2-437d-43ad-81dc-759f943c365d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156054416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.156054416
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.1591760403
Short name T362
Test name
Test status
Simulation time 105921786 ps
CPU time 0.98 seconds
Started Aug 19 05:22:34 PM PDT 24
Finished Aug 19 05:22:35 PM PDT 24
Peak memory 196376 kb
Host smart-ff3e9b78-d236-41b2-b881-f38c62fb0d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591760403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1591760403
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3137618403
Short name T209
Test name
Test status
Simulation time 175323256 ps
CPU time 1.29 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 195704 kb
Host smart-8c90a4f6-e906-4ad0-8870-f228d963b724
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137618403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3137618403
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1729248407
Short name T299
Test name
Test status
Simulation time 1884914220 ps
CPU time 46.67 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:23:31 PM PDT 24
Peak memory 198188 kb
Host smart-7e512d9f-2df8-4254-ab37-471b79325e65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729248407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1729248407
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3983145046
Short name T254
Test name
Test status
Simulation time 12939771 ps
CPU time 0.57 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:09 PM PDT 24
Peak memory 193764 kb
Host smart-0b9bb327-c4b3-4e48-b603-ffa7a04eac90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983145046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3983145046
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.594124382
Short name T618
Test name
Test status
Simulation time 460221361 ps
CPU time 0.9 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 197280 kb
Host smart-3658b75a-aafb-4810-b70f-aff2637985a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594124382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.594124382
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2750632579
Short name T187
Test name
Test status
Simulation time 243241556 ps
CPU time 10.53 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:16 PM PDT 24
Peak memory 198152 kb
Host smart-47a5154d-4bc9-4229-891c-4f56c617f318
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750632579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2750632579
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.563076336
Short name T363
Test name
Test status
Simulation time 81361191 ps
CPU time 0.94 seconds
Started Aug 19 05:25:07 PM PDT 24
Finished Aug 19 05:25:08 PM PDT 24
Peak memory 196240 kb
Host smart-bb6031db-de2a-4980-93a0-60defdc49a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563076336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.563076336
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.4292516512
Short name T161
Test name
Test status
Simulation time 22575854 ps
CPU time 0.7 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 194484 kb
Host smart-37a09212-2bb3-4eea-a76b-2fb09d1855d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292516512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.4292516512
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3901957140
Short name T671
Test name
Test status
Simulation time 32606333 ps
CPU time 1.44 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:09 PM PDT 24
Peak memory 196624 kb
Host smart-88d51469-8213-4fdc-a7e5-c74499b71d1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901957140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3901957140
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1261157935
Short name T344
Test name
Test status
Simulation time 697948725 ps
CPU time 2.65 seconds
Started Aug 19 05:25:05 PM PDT 24
Finished Aug 19 05:25:08 PM PDT 24
Peak memory 197308 kb
Host smart-8cc477fa-8e7f-4d1d-8d89-96838d038655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261157935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1261157935
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1869511409
Short name T637
Test name
Test status
Simulation time 15234860 ps
CPU time 0.71 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 195212 kb
Host smart-4e67e92d-47b8-4a57-a08d-b6bb231d518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869511409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1869511409
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4079117856
Short name T573
Test name
Test status
Simulation time 41050918 ps
CPU time 0.98 seconds
Started Aug 19 05:25:05 PM PDT 24
Finished Aug 19 05:25:06 PM PDT 24
Peak memory 196216 kb
Host smart-4b9b0ca9-5b7a-4b4f-bf96-2874327ea39b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079117856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4079117856
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.782700213
Short name T525
Test name
Test status
Simulation time 1421924489 ps
CPU time 2.18 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:08 PM PDT 24
Peak memory 198080 kb
Host smart-22b4bbf0-c714-4422-b59c-840069409e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782700213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.782700213
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3315448910
Short name T500
Test name
Test status
Simulation time 101961026 ps
CPU time 1.46 seconds
Started Aug 19 05:25:04 PM PDT 24
Finished Aug 19 05:25:05 PM PDT 24
Peak memory 195684 kb
Host smart-b3bd82a2-eaa4-47e4-b763-d57b943891e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315448910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3315448910
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.299414125
Short name T563
Test name
Test status
Simulation time 124584237 ps
CPU time 0.85 seconds
Started Aug 19 05:25:06 PM PDT 24
Finished Aug 19 05:25:07 PM PDT 24
Peak memory 196364 kb
Host smart-69562382-7341-4d30-bf7a-608e1f090dd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299414125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.299414125
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.345492607
Short name T3
Test name
Test status
Simulation time 65943350697 ps
CPU time 188.62 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:28:16 PM PDT 24
Peak memory 198352 kb
Host smart-fc902e1a-98a1-4fca-b132-c1ed699f52f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345492607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.345492607
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3942270365
Short name T448
Test name
Test status
Simulation time 19942692565 ps
CPU time 171.06 seconds
Started Aug 19 05:25:07 PM PDT 24
Finished Aug 19 05:27:59 PM PDT 24
Peak memory 198512 kb
Host smart-768ddbaa-6a91-474c-b181-09aea08165db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3942270365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3942270365
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1095310001
Short name T140
Test name
Test status
Simulation time 15041413 ps
CPU time 0.58 seconds
Started Aug 19 05:25:20 PM PDT 24
Finished Aug 19 05:25:20 PM PDT 24
Peak memory 194792 kb
Host smart-9fd06773-bc57-42f9-963a-d14ecebcd075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095310001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1095310001
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3655499395
Short name T157
Test name
Test status
Simulation time 40522010 ps
CPU time 0.75 seconds
Started Aug 19 05:25:10 PM PDT 24
Finished Aug 19 05:25:10 PM PDT 24
Peak memory 195456 kb
Host smart-fc4bbbdd-c2a4-42b7-a4a7-502bdb80b29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655499395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3655499395
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2223998926
Short name T151
Test name
Test status
Simulation time 2084233199 ps
CPU time 18.64 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:26 PM PDT 24
Peak memory 198188 kb
Host smart-fc9fbb1d-ea4b-42db-ae32-e84ae0f13648
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223998926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2223998926
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1780792766
Short name T4
Test name
Test status
Simulation time 1092620461 ps
CPU time 0.97 seconds
Started Aug 19 05:25:09 PM PDT 24
Finished Aug 19 05:25:10 PM PDT 24
Peak memory 197984 kb
Host smart-f647f3d4-93e6-46c4-acdc-8612ef0ce5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780792766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1780792766
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.59692758
Short name T704
Test name
Test status
Simulation time 67046127 ps
CPU time 1.15 seconds
Started Aug 19 05:25:05 PM PDT 24
Finished Aug 19 05:25:06 PM PDT 24
Peak memory 196056 kb
Host smart-c379b20a-bc36-4ffa-8e5a-c73c07262dc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59692758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.59692758
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.648612009
Short name T288
Test name
Test status
Simulation time 187885824 ps
CPU time 3.71 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:12 PM PDT 24
Peak memory 198216 kb
Host smart-0dc3402f-c13a-4235-8dcd-e7232fcd607d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648612009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.648612009
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.520722833
Short name T650
Test name
Test status
Simulation time 95247881 ps
CPU time 1.88 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:10 PM PDT 24
Peak memory 195984 kb
Host smart-e98239a9-1575-437f-8904-1a0a5832db05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520722833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
520722833
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2065610508
Short name T186
Test name
Test status
Simulation time 70382791 ps
CPU time 1.01 seconds
Started Aug 19 05:25:13 PM PDT 24
Finished Aug 19 05:25:14 PM PDT 24
Peak memory 196164 kb
Host smart-f761eaaa-6945-4342-b8fe-d9df15359cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065610508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2065610508
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3867041354
Short name T208
Test name
Test status
Simulation time 23568137 ps
CPU time 0.96 seconds
Started Aug 19 05:25:07 PM PDT 24
Finished Aug 19 05:25:08 PM PDT 24
Peak memory 195980 kb
Host smart-11477449-372d-44c0-9681-771fdae97431
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867041354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3867041354
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4119994432
Short name T290
Test name
Test status
Simulation time 474834351 ps
CPU time 5.54 seconds
Started Aug 19 05:25:08 PM PDT 24
Finished Aug 19 05:25:14 PM PDT 24
Peak memory 198164 kb
Host smart-271aebd4-bde7-475d-893a-66430bf65b82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119994432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4119994432
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1958078384
Short name T204
Test name
Test status
Simulation time 44916827 ps
CPU time 0.95 seconds
Started Aug 19 05:25:07 PM PDT 24
Finished Aug 19 05:25:08 PM PDT 24
Peak memory 197152 kb
Host smart-8b124537-b809-43b5-b019-020dcf3777ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958078384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1958078384
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.907087809
Short name T306
Test name
Test status
Simulation time 183935180 ps
CPU time 1.38 seconds
Started Aug 19 05:25:07 PM PDT 24
Finished Aug 19 05:25:08 PM PDT 24
Peak memory 197060 kb
Host smart-a1f4cbb5-0d73-447c-a38b-b6b78bc9522d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907087809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.907087809
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3658778147
Short name T437
Test name
Test status
Simulation time 9954435590 ps
CPU time 141.26 seconds
Started Aug 19 05:25:16 PM PDT 24
Finished Aug 19 05:27:38 PM PDT 24
Peak memory 198420 kb
Host smart-47d9968a-ce07-431f-a358-dcc3a63435fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658778147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3658778147
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.4055934918
Short name T461
Test name
Test status
Simulation time 20862739 ps
CPU time 0.59 seconds
Started Aug 19 05:25:13 PM PDT 24
Finished Aug 19 05:25:14 PM PDT 24
Peak memory 194136 kb
Host smart-823c9c07-bcb2-44c3-a8b0-6be7ae6ff047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055934918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.4055934918
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2845859768
Short name T619
Test name
Test status
Simulation time 34304801 ps
CPU time 0.81 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 196236 kb
Host smart-1984f937-490f-406e-9844-96316c1cd8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845859768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2845859768
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2444488235
Short name T29
Test name
Test status
Simulation time 717953986 ps
CPU time 24.29 seconds
Started Aug 19 05:25:16 PM PDT 24
Finished Aug 19 05:25:40 PM PDT 24
Peak memory 198144 kb
Host smart-0359d11c-3baf-416f-ae15-5207552223e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444488235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2444488235
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1977905291
Short name T372
Test name
Test status
Simulation time 88187345 ps
CPU time 0.97 seconds
Started Aug 19 05:25:14 PM PDT 24
Finished Aug 19 05:25:15 PM PDT 24
Peak memory 196684 kb
Host smart-c994fe6e-1ed2-481b-9c0c-bde8e69f41dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977905291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1977905291
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3767683689
Short name T125
Test name
Test status
Simulation time 171634398 ps
CPU time 1.42 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 197268 kb
Host smart-99e00b1b-bc8d-464c-808f-12b016096a87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767683689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3767683689
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3914945354
Short name T520
Test name
Test status
Simulation time 194317451 ps
CPU time 1.6 seconds
Started Aug 19 05:25:15 PM PDT 24
Finished Aug 19 05:25:17 PM PDT 24
Peak memory 198276 kb
Host smart-a3961d2a-068c-48f5-b4ed-2e0133adff09
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914945354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3914945354
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.4020493088
Short name T105
Test name
Test status
Simulation time 403490339 ps
CPU time 1.1 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 195760 kb
Host smart-161d2036-b7cc-4660-acb8-67b2f36555ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020493088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.4020493088
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3310559965
Short name T553
Test name
Test status
Simulation time 37583096 ps
CPU time 0.7 seconds
Started Aug 19 05:25:16 PM PDT 24
Finished Aug 19 05:25:17 PM PDT 24
Peak memory 195112 kb
Host smart-7eb56c1d-27ac-46f1-b2d1-ae21d19958c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310559965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3310559965
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3685493836
Short name T471
Test name
Test status
Simulation time 20997612 ps
CPU time 0.71 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 195172 kb
Host smart-6acf663d-fe33-4093-9e46-dfd41a24dc9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685493836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3685493836
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1557997991
Short name T5
Test name
Test status
Simulation time 263113025 ps
CPU time 2 seconds
Started Aug 19 05:25:16 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 198184 kb
Host smart-06e55f50-ce6f-45b2-b64a-2d8a302f88c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557997991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1557997991
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2147997055
Short name T398
Test name
Test status
Simulation time 62254410 ps
CPU time 0.98 seconds
Started Aug 19 05:25:15 PM PDT 24
Finished Aug 19 05:25:16 PM PDT 24
Peak memory 196480 kb
Host smart-3ed623c0-95c1-47a1-ae25-90d2f2f4220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147997055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2147997055
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3726783685
Short name T330
Test name
Test status
Simulation time 148940857 ps
CPU time 0.9 seconds
Started Aug 19 05:25:15 PM PDT 24
Finished Aug 19 05:25:16 PM PDT 24
Peak memory 196360 kb
Host smart-d0fcc795-39b3-4c7a-97b7-b8fbde6b88a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726783685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3726783685
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.711328147
Short name T591
Test name
Test status
Simulation time 7429938079 ps
CPU time 221.16 seconds
Started Aug 19 05:25:16 PM PDT 24
Finished Aug 19 05:28:58 PM PDT 24
Peak memory 198368 kb
Host smart-7d68df58-1eb5-4d50-95d8-f8b2ef98ba1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711328147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.711328147
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1210599104
Short name T469
Test name
Test status
Simulation time 19849952156 ps
CPU time 161.7 seconds
Started Aug 19 05:25:15 PM PDT 24
Finished Aug 19 05:27:57 PM PDT 24
Peak memory 198572 kb
Host smart-e96d73bc-789c-4aff-a849-12765176a57e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1210599104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1210599104
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.168620128
Short name T212
Test name
Test status
Simulation time 25203395 ps
CPU time 0.56 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:28 PM PDT 24
Peak memory 194072 kb
Host smart-cbb8153a-d26c-4d78-8620-a4b9a0a112f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168620128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.168620128
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3348872222
Short name T572
Test name
Test status
Simulation time 48313421 ps
CPU time 0.61 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 194052 kb
Host smart-9628d692-c7ad-4dee-88cc-0560b9678e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348872222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3348872222
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.409600758
Short name T449
Test name
Test status
Simulation time 1575060488 ps
CPU time 22.54 seconds
Started Aug 19 05:25:14 PM PDT 24
Finished Aug 19 05:25:37 PM PDT 24
Peak memory 198168 kb
Host smart-cb77206f-1e33-4cd6-bd3a-712806953db4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409600758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.409600758
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3350151435
Short name T6
Test name
Test status
Simulation time 317388271 ps
CPU time 1.02 seconds
Started Aug 19 05:25:15 PM PDT 24
Finished Aug 19 05:25:16 PM PDT 24
Peak memory 198064 kb
Host smart-2d4b84d2-d8de-4a73-ba48-ea26c2e6d907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350151435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3350151435
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3672290069
Short name T328
Test name
Test status
Simulation time 24644804 ps
CPU time 0.87 seconds
Started Aug 19 05:25:14 PM PDT 24
Finished Aug 19 05:25:15 PM PDT 24
Peak memory 195648 kb
Host smart-3a8fc075-95ca-4a79-8bcb-e475cc1763fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672290069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3672290069
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3785711990
Short name T480
Test name
Test status
Simulation time 285269924 ps
CPU time 1.54 seconds
Started Aug 19 05:25:18 PM PDT 24
Finished Aug 19 05:25:19 PM PDT 24
Peak memory 198184 kb
Host smart-d3fe7b3e-d207-483d-bc7d-e9e769549b5b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785711990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3785711990
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.157879104
Short name T167
Test name
Test status
Simulation time 334863559 ps
CPU time 2.64 seconds
Started Aug 19 05:25:16 PM PDT 24
Finished Aug 19 05:25:19 PM PDT 24
Peak memory 197304 kb
Host smart-e070d52e-5120-45a1-bb70-5d7a5d860ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157879104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
157879104
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3720344821
Short name T205
Test name
Test status
Simulation time 317335838 ps
CPU time 0.94 seconds
Started Aug 19 05:25:16 PM PDT 24
Finished Aug 19 05:25:17 PM PDT 24
Peak memory 196076 kb
Host smart-618ff7ef-277b-414b-aa76-46f7a02dcb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720344821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3720344821
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2758654174
Short name T356
Test name
Test status
Simulation time 218111202 ps
CPU time 1.07 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 196012 kb
Host smart-2d47cb79-499a-49fc-9ced-bace750c4e04
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758654174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2758654174
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2856793958
Short name T442
Test name
Test status
Simulation time 347623164 ps
CPU time 3.93 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:21 PM PDT 24
Peak memory 198184 kb
Host smart-59611038-1165-4bef-a8a8-6bb9772184b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856793958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2856793958
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3956283840
Short name T269
Test name
Test status
Simulation time 187646525 ps
CPU time 0.94 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:25:18 PM PDT 24
Peak memory 196680 kb
Host smart-6e48c8d9-4c16-4c15-9a2f-3c8b1b6cb56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956283840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3956283840
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1735667410
Short name T142
Test name
Test status
Simulation time 217315160 ps
CPU time 1.4 seconds
Started Aug 19 05:25:19 PM PDT 24
Finished Aug 19 05:25:21 PM PDT 24
Peak memory 196980 kb
Host smart-3af3b33c-d5b0-463d-9be9-5b4588c95896
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735667410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1735667410
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1741293163
Short name T512
Test name
Test status
Simulation time 12128021041 ps
CPU time 84.43 seconds
Started Aug 19 05:25:17 PM PDT 24
Finished Aug 19 05:26:42 PM PDT 24
Peak memory 198372 kb
Host smart-d9628902-2e94-4208-bd2f-a58f2f13fb68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741293163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1741293163
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.4007186342
Short name T233
Test name
Test status
Simulation time 12426216 ps
CPU time 0.61 seconds
Started Aug 19 05:25:30 PM PDT 24
Finished Aug 19 05:25:31 PM PDT 24
Peak memory 194036 kb
Host smart-3f62ced3-dafc-44ec-8616-be88a6aeae28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007186342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.4007186342
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4062877159
Short name T170
Test name
Test status
Simulation time 16378033 ps
CPU time 0.68 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:28 PM PDT 24
Peak memory 194236 kb
Host smart-13eb0448-a47b-42b1-a799-2d9a99678762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062877159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4062877159
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1708380480
Short name T123
Test name
Test status
Simulation time 615096524 ps
CPU time 17.44 seconds
Started Aug 19 05:25:24 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 197176 kb
Host smart-2c44592c-2956-4ed5-afe2-d4753d24a6bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708380480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1708380480
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3121669501
Short name T207
Test name
Test status
Simulation time 125422893 ps
CPU time 0.92 seconds
Started Aug 19 05:25:29 PM PDT 24
Finished Aug 19 05:25:30 PM PDT 24
Peak memory 196256 kb
Host smart-f2a4aefa-86d1-407c-8a7e-3ffdd6a27fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121669501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3121669501
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2780765189
Short name T213
Test name
Test status
Simulation time 84423225 ps
CPU time 0.97 seconds
Started Aug 19 05:25:30 PM PDT 24
Finished Aug 19 05:25:31 PM PDT 24
Peak memory 197012 kb
Host smart-bfc66117-7760-496a-88c1-6ce4e74caa4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780765189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2780765189
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2938097935
Short name T703
Test name
Test status
Simulation time 80104459 ps
CPU time 3.18 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:30 PM PDT 24
Peak memory 198176 kb
Host smart-2d308370-c937-4f70-b002-2c2fc02295df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938097935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2938097935
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1694053460
Short name T158
Test name
Test status
Simulation time 440904504 ps
CPU time 2.33 seconds
Started Aug 19 05:25:30 PM PDT 24
Finished Aug 19 05:25:33 PM PDT 24
Peak memory 195972 kb
Host smart-da4d8aaa-8fd7-46e0-8778-00204e41ebfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694053460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1694053460
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2086066682
Short name T17
Test name
Test status
Simulation time 78359014 ps
CPU time 1.07 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:27 PM PDT 24
Peak memory 196024 kb
Host smart-4d8e7c63-b37d-44bc-a7c8-fd04923d5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086066682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2086066682
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3739222483
Short name T589
Test name
Test status
Simulation time 33959961 ps
CPU time 0.95 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 196876 kb
Host smart-4d542cb4-4671-4051-a4e4-43af199d1127
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739222483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3739222483
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3216845431
Short name T485
Test name
Test status
Simulation time 237596295 ps
CPU time 3.2 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:32 PM PDT 24
Peak memory 198116 kb
Host smart-fa994bda-0db8-4746-82b1-8a68f9954cb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216845431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3216845431
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1520396193
Short name T294
Test name
Test status
Simulation time 200023373 ps
CPU time 0.96 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 197244 kb
Host smart-7ff36af6-9295-45da-b80e-98716a8d2c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520396193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1520396193
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2141107007
Short name T687
Test name
Test status
Simulation time 40196444 ps
CPU time 1.02 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 195936 kb
Host smart-14716c2f-3857-43bc-bc37-b07a029dc7c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141107007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2141107007
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.436310929
Short name T513
Test name
Test status
Simulation time 3041367693 ps
CPU time 75.52 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:26:42 PM PDT 24
Peak memory 198388 kb
Host smart-bd39f14c-d11e-4012-bab8-5b322e46c840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436310929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.436310929
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1943339577
Short name T598
Test name
Test status
Simulation time 4373538533 ps
CPU time 148.51 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:27:55 PM PDT 24
Peak memory 198552 kb
Host smart-69ab8e3f-6e2f-4f55-8e49-10e0ebed6912
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1943339577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1943339577
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1609593098
Short name T670
Test name
Test status
Simulation time 11680499 ps
CPU time 0.55 seconds
Started Aug 19 05:25:29 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 194784 kb
Host smart-53068001-bd33-4400-8be3-bc3a327a98bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609593098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1609593098
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3388945882
Short name T214
Test name
Test status
Simulation time 44469512 ps
CPU time 0.63 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:27 PM PDT 24
Peak memory 194800 kb
Host smart-2bd9a4c0-94c5-4439-98e7-0fc565b1bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388945882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3388945882
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2072658724
Short name T621
Test name
Test status
Simulation time 242832059 ps
CPU time 8.95 seconds
Started Aug 19 05:25:29 PM PDT 24
Finished Aug 19 05:25:38 PM PDT 24
Peak memory 196880 kb
Host smart-03c85eeb-0290-4ee1-ab72-bba2b42c143b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072658724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2072658724
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1262081392
Short name T28
Test name
Test status
Simulation time 136157933 ps
CPU time 0.88 seconds
Started Aug 19 05:25:30 PM PDT 24
Finished Aug 19 05:25:31 PM PDT 24
Peak memory 197236 kb
Host smart-555e45ee-8d0f-4ffe-894e-720d69382f9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262081392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1262081392
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2190460660
Short name T394
Test name
Test status
Simulation time 139471626 ps
CPU time 0.88 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:28 PM PDT 24
Peak memory 197484 kb
Host smart-82781b5f-5484-4272-a916-9703b4f05aae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190460660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2190460660
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1711156642
Short name T229
Test name
Test status
Simulation time 126907571 ps
CPU time 1.13 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:28 PM PDT 24
Peak memory 198028 kb
Host smart-d40c5afa-9fc2-4e05-969d-52ae0449a939
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711156642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1711156642
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2599149933
Short name T494
Test name
Test status
Simulation time 81337734 ps
CPU time 1.87 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 196024 kb
Host smart-e21db40a-c58d-4aa9-a74a-80b6028ba81d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599149933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2599149933
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.751485686
Short name T353
Test name
Test status
Simulation time 93113852 ps
CPU time 0.8 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:27 PM PDT 24
Peak memory 195472 kb
Host smart-ed18c011-b8ce-45b1-b34d-13ec10dcd027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751485686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.751485686
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1427920183
Short name T514
Test name
Test status
Simulation time 33049269 ps
CPU time 0.92 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:28 PM PDT 24
Peak memory 196760 kb
Host smart-106befde-9cd1-465d-b68e-8aa30269683a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427920183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1427920183
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3600052570
Short name T580
Test name
Test status
Simulation time 3153990802 ps
CPU time 4.87 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:31 PM PDT 24
Peak memory 198328 kb
Host smart-c2ffb029-b396-4b64-9c07-5de20beb2019
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600052570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3600052570
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2694125883
Short name T238
Test name
Test status
Simulation time 61758005 ps
CPU time 1.19 seconds
Started Aug 19 05:25:24 PM PDT 24
Finished Aug 19 05:25:25 PM PDT 24
Peak memory 196464 kb
Host smart-b00771be-75f5-4717-bd71-dae8bb2cfde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694125883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2694125883
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2411821114
Short name T251
Test name
Test status
Simulation time 511779540 ps
CPU time 1.16 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 198116 kb
Host smart-6e9bc132-79c6-407f-8961-2de222d9677e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411821114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2411821114
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1969671509
Short name T473
Test name
Test status
Simulation time 5663883362 ps
CPU time 148.13 seconds
Started Aug 19 05:25:25 PM PDT 24
Finished Aug 19 05:27:54 PM PDT 24
Peak memory 198388 kb
Host smart-76780ac1-2edc-4ffb-afcf-16c99950efc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969671509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1969671509
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1551948500
Short name T224
Test name
Test status
Simulation time 4811858727 ps
CPU time 72.97 seconds
Started Aug 19 05:25:29 PM PDT 24
Finished Aug 19 05:26:42 PM PDT 24
Peak memory 198536 kb
Host smart-e4a971f2-1dce-44b0-9630-92e5570a25b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1551948500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1551948500
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2479367875
Short name T639
Test name
Test status
Simulation time 47850694 ps
CPU time 0.61 seconds
Started Aug 19 05:25:38 PM PDT 24
Finished Aug 19 05:25:39 PM PDT 24
Peak memory 194116 kb
Host smart-21552a70-86f1-45cb-b489-6dbd1cdbbe56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479367875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2479367875
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3272741636
Short name T415
Test name
Test status
Simulation time 56582694 ps
CPU time 0.91 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:27 PM PDT 24
Peak memory 197176 kb
Host smart-1a971427-35c5-417f-afed-6159e2e10b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272741636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3272741636
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2615932464
Short name T543
Test name
Test status
Simulation time 768482540 ps
CPU time 5.56 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:34 PM PDT 24
Peak memory 195672 kb
Host smart-6c2c98b7-35ec-45cb-95ca-8f1bae95d60e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615932464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2615932464
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3871217566
Short name T431
Test name
Test status
Simulation time 201697018 ps
CPU time 1 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:27 PM PDT 24
Peak memory 196672 kb
Host smart-4635564a-8b63-4b6a-8981-c199b63cb035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871217566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3871217566
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2358742029
Short name T658
Test name
Test status
Simulation time 256428555 ps
CPU time 1.14 seconds
Started Aug 19 05:25:29 PM PDT 24
Finished Aug 19 05:25:30 PM PDT 24
Peak memory 196320 kb
Host smart-6a64db28-d4f5-4074-b681-6d886086764a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358742029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2358742029
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1726893048
Short name T197
Test name
Test status
Simulation time 612562015 ps
CPU time 3.24 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:31 PM PDT 24
Peak memory 198184 kb
Host smart-b515991f-6a71-4f6f-b3a7-2e3a123f1437
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726893048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1726893048
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.349009894
Short name T296
Test name
Test status
Simulation time 159168674 ps
CPU time 1.97 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 196192 kb
Host smart-594ea6a9-0e36-4479-a14e-092fcbd3011c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349009894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
349009894
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.332558382
Short name T285
Test name
Test status
Simulation time 200634464 ps
CPU time 1.34 seconds
Started Aug 19 05:25:27 PM PDT 24
Finished Aug 19 05:25:28 PM PDT 24
Peak memory 197208 kb
Host smart-bf8d975e-f4f2-4426-961e-19be57b59c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332558382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.332558382
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.765218391
Short name T424
Test name
Test status
Simulation time 72844767 ps
CPU time 1.35 seconds
Started Aug 19 05:25:32 PM PDT 24
Finished Aug 19 05:25:33 PM PDT 24
Peak memory 197176 kb
Host smart-d297ca98-c458-4d42-8cae-09fed95e513c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765218391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.765218391
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2962016153
Short name T21
Test name
Test status
Simulation time 1928738422 ps
CPU time 6.2 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:32 PM PDT 24
Peak memory 198180 kb
Host smart-23820cff-77b4-45dc-aaea-bd8e8946b166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962016153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2962016153
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1090519502
Short name T602
Test name
Test status
Simulation time 61619523 ps
CPU time 1.21 seconds
Started Aug 19 05:25:28 PM PDT 24
Finished Aug 19 05:25:29 PM PDT 24
Peak memory 196044 kb
Host smart-d556633d-9c18-4704-909d-b8a1c61b74a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090519502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1090519502
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2486564656
Short name T549
Test name
Test status
Simulation time 155632637 ps
CPU time 1.01 seconds
Started Aug 19 05:25:26 PM PDT 24
Finished Aug 19 05:25:27 PM PDT 24
Peak memory 196596 kb
Host smart-14f78cdd-c798-4715-92fa-40b07ed1deae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486564656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2486564656
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3752029019
Short name T439
Test name
Test status
Simulation time 18039369526 ps
CPU time 202.97 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:29:03 PM PDT 24
Peak memory 198376 kb
Host smart-0318a4b3-e9f5-46fb-99c7-cbbef5c673c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752029019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3752029019
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.4091637421
Short name T379
Test name
Test status
Simulation time 14192060 ps
CPU time 0.57 seconds
Started Aug 19 05:25:44 PM PDT 24
Finished Aug 19 05:25:45 PM PDT 24
Peak memory 194232 kb
Host smart-05ec6e7d-3b99-4144-af3f-ebbc04948132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091637421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4091637421
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4070758812
Short name T92
Test name
Test status
Simulation time 289439695 ps
CPU time 0.84 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:41 PM PDT 24
Peak memory 195552 kb
Host smart-1a56508d-3c1f-4ca0-825a-4de4d3ab7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070758812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.4070758812
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3340790200
Short name T338
Test name
Test status
Simulation time 252475873 ps
CPU time 6.43 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:46 PM PDT 24
Peak memory 196880 kb
Host smart-7372fea4-516d-41ae-9745-1a4e7de89e39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340790200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3340790200
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1764790056
Short name T506
Test name
Test status
Simulation time 206433004 ps
CPU time 1.23 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:43 PM PDT 24
Peak memory 196780 kb
Host smart-13605cef-4925-4816-8945-cb8126a7d709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764790056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1764790056
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.437809884
Short name T519
Test name
Test status
Simulation time 89800990 ps
CPU time 0.92 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 195992 kb
Host smart-f171f44f-dc1b-4e81-9e46-4ed22c0df8d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437809884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.437809884
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3342807749
Short name T477
Test name
Test status
Simulation time 529728906 ps
CPU time 3.51 seconds
Started Aug 19 05:25:42 PM PDT 24
Finished Aug 19 05:25:45 PM PDT 24
Peak memory 198164 kb
Host smart-fda24f61-e38c-4c7f-a58e-5f187927e179
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342807749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3342807749
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1001866351
Short name T440
Test name
Test status
Simulation time 64593948 ps
CPU time 2.08 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 197396 kb
Host smart-ffddd3b7-03e5-4284-9ace-9ec2cd3a3276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001866351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1001866351
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2313333261
Short name T287
Test name
Test status
Simulation time 65780013 ps
CPU time 0.67 seconds
Started Aug 19 05:25:36 PM PDT 24
Finished Aug 19 05:25:36 PM PDT 24
Peak memory 194416 kb
Host smart-7731f301-8821-4d0f-aa5d-fa3ab5885b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313333261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2313333261
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.4112124404
Short name T673
Test name
Test status
Simulation time 64220474 ps
CPU time 0.81 seconds
Started Aug 19 05:25:39 PM PDT 24
Finished Aug 19 05:25:40 PM PDT 24
Peak memory 195728 kb
Host smart-8e1bbfda-0788-4667-980e-5c77b0484ce4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112124404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.4112124404
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3704888223
Short name T234
Test name
Test status
Simulation time 239185551 ps
CPU time 2.84 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:43 PM PDT 24
Peak memory 198216 kb
Host smart-3972e634-dfe8-4f86-9eb4-244d3d9161ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704888223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3704888223
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1541236405
Short name T272
Test name
Test status
Simulation time 85026342 ps
CPU time 0.88 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:41 PM PDT 24
Peak memory 195364 kb
Host smart-8187f38a-ab87-482d-bd3a-a42fb57dcfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541236405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1541236405
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3473321270
Short name T324
Test name
Test status
Simulation time 25737281 ps
CPU time 0.76 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 194984 kb
Host smart-2204eb05-3e3d-4cbd-9e9b-8e1330816abd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473321270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3473321270
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1081376892
Short name T94
Test name
Test status
Simulation time 32646041685 ps
CPU time 208.68 seconds
Started Aug 19 05:25:45 PM PDT 24
Finished Aug 19 05:29:13 PM PDT 24
Peak memory 198340 kb
Host smart-c8378886-361e-4107-9418-44c9be14ebff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081376892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1081376892
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1022291154
Short name T444
Test name
Test status
Simulation time 181582392 ps
CPU time 0.58 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:41 PM PDT 24
Peak memory 194972 kb
Host smart-2753ba89-58d2-4ec7-baa9-ee00615fe775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022291154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1022291154
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1347180285
Short name T606
Test name
Test status
Simulation time 164163443 ps
CPU time 0.91 seconds
Started Aug 19 05:25:37 PM PDT 24
Finished Aug 19 05:25:38 PM PDT 24
Peak memory 196076 kb
Host smart-9e908a9e-1867-4ad6-a181-4129f325e272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347180285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1347180285
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1218993696
Short name T631
Test name
Test status
Simulation time 775708103 ps
CPU time 21.5 seconds
Started Aug 19 05:25:38 PM PDT 24
Finished Aug 19 05:26:00 PM PDT 24
Peak memory 197156 kb
Host smart-66f45126-a54e-45c2-a532-f6418c7d1de7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218993696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1218993696
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2341553406
Short name T524
Test name
Test status
Simulation time 131618528 ps
CPU time 0.73 seconds
Started Aug 19 05:25:39 PM PDT 24
Finished Aug 19 05:25:39 PM PDT 24
Peak memory 195876 kb
Host smart-2041fdcc-f17d-410e-99ce-6a72d4822bdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341553406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2341553406
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1885509825
Short name T339
Test name
Test status
Simulation time 57434270 ps
CPU time 0.99 seconds
Started Aug 19 05:25:42 PM PDT 24
Finished Aug 19 05:25:43 PM PDT 24
Peak memory 196284 kb
Host smart-57a6401a-a4fa-411c-a8a0-801662d45c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885509825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1885509825
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.459076982
Short name T597
Test name
Test status
Simulation time 22611902 ps
CPU time 1.07 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 196156 kb
Host smart-6b852c20-6fed-4be6-aad0-75258d627423
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459076982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.459076982
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2820312726
Short name T368
Test name
Test status
Simulation time 180896995 ps
CPU time 1.82 seconds
Started Aug 19 05:25:38 PM PDT 24
Finished Aug 19 05:25:40 PM PDT 24
Peak memory 196980 kb
Host smart-6be26c66-fa3a-43d8-bd9f-8548e7fa3140
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820312726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2820312726
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.452442445
Short name T300
Test name
Test status
Simulation time 17975695 ps
CPU time 0.7 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:41 PM PDT 24
Peak memory 195272 kb
Host smart-37455610-edd4-4f57-8adb-7b3381b90e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452442445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.452442445
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4081404331
Short name T159
Test name
Test status
Simulation time 30681733 ps
CPU time 0.81 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:41 PM PDT 24
Peak memory 195500 kb
Host smart-71975d86-d0fb-4686-b93c-b445c258a90b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081404331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4081404331
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.438007373
Short name T689
Test name
Test status
Simulation time 376024491 ps
CPU time 4.67 seconds
Started Aug 19 05:25:37 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 198168 kb
Host smart-72868ddd-fe54-4bb6-be47-9205c2215ff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438007373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.438007373
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3667550577
Short name T135
Test name
Test status
Simulation time 448994642 ps
CPU time 0.92 seconds
Started Aug 19 05:25:38 PM PDT 24
Finished Aug 19 05:25:39 PM PDT 24
Peak memory 195532 kb
Host smart-7a10b1f6-9c4f-44f9-b14b-6325ecf58ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667550577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3667550577
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3844643945
Short name T532
Test name
Test status
Simulation time 40151193 ps
CPU time 1.22 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:41 PM PDT 24
Peak memory 196484 kb
Host smart-d5ef98cf-52a9-474b-95fd-72758de721f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844643945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3844643945
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2886223319
Short name T640
Test name
Test status
Simulation time 78714117346 ps
CPU time 207.64 seconds
Started Aug 19 05:25:37 PM PDT 24
Finished Aug 19 05:29:05 PM PDT 24
Peak memory 198328 kb
Host smart-5f0454ce-a93d-4215-8ab0-83809c3b12bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886223319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2886223319
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1556080472
Short name T63
Test name
Test status
Simulation time 3613891005 ps
CPU time 72.69 seconds
Started Aug 19 05:25:39 PM PDT 24
Finished Aug 19 05:26:52 PM PDT 24
Peak memory 198516 kb
Host smart-1086c0fa-3b13-4707-985a-554897bcc42f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1556080472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1556080472
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.611451403
Short name T586
Test name
Test status
Simulation time 32100945 ps
CPU time 0.56 seconds
Started Aug 19 05:25:42 PM PDT 24
Finished Aug 19 05:25:43 PM PDT 24
Peak memory 194052 kb
Host smart-de39bfc5-892b-4995-9e7d-a8e79bd4df60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611451403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.611451403
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.179070473
Short name T557
Test name
Test status
Simulation time 21221330 ps
CPU time 0.72 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 195020 kb
Host smart-162ec624-88ed-4d4d-8c79-7b3cc22d8d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179070473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.179070473
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.501858378
Short name T271
Test name
Test status
Simulation time 494756402 ps
CPU time 12.85 seconds
Started Aug 19 05:25:39 PM PDT 24
Finished Aug 19 05:25:52 PM PDT 24
Peak memory 197028 kb
Host smart-dfd0a4e2-a12c-46e5-b6f2-afbf1d5ad3e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501858378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.501858378
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3252336972
Short name T131
Test name
Test status
Simulation time 149598424 ps
CPU time 0.76 seconds
Started Aug 19 05:25:37 PM PDT 24
Finished Aug 19 05:25:37 PM PDT 24
Peak memory 195860 kb
Host smart-146fea6f-51dd-42d6-a689-8bf552894359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252336972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3252336972
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1298390633
Short name T230
Test name
Test status
Simulation time 106790836 ps
CPU time 1.63 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:43 PM PDT 24
Peak memory 197224 kb
Host smart-622b35be-49bc-4eed-b238-669f12458719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298390633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1298390633
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1856549364
Short name T696
Test name
Test status
Simulation time 162718484 ps
CPU time 3.52 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:44 PM PDT 24
Peak memory 198188 kb
Host smart-0b5420ea-5656-4237-858c-6e42d721dcad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856549364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1856549364
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1288873937
Short name T530
Test name
Test status
Simulation time 197605138 ps
CPU time 1.26 seconds
Started Aug 19 05:25:40 PM PDT 24
Finished Aug 19 05:25:42 PM PDT 24
Peak memory 195636 kb
Host smart-0461f71b-5761-4515-896f-64b0476e1523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288873937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1288873937
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3412291689
Short name T655
Test name
Test status
Simulation time 34736668 ps
CPU time 1.37 seconds
Started Aug 19 05:25:39 PM PDT 24
Finished Aug 19 05:25:40 PM PDT 24
Peak memory 197200 kb
Host smart-3c53ab60-3eb3-428a-a8a0-11c470f58e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412291689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3412291689
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.786857488
Short name T625
Test name
Test status
Simulation time 36074114 ps
CPU time 1.37 seconds
Started Aug 19 05:25:41 PM PDT 24
Finished Aug 19 05:25:43 PM PDT 24
Peak memory 196712 kb
Host smart-cd0034c2-3682-4ce0-9843-6f89dc261a80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786857488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.786857488
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.346727391
Short name T293
Test name
Test status
Simulation time 533167888 ps
CPU time 2.41 seconds
Started Aug 19 05:25:42 PM PDT 24
Finished Aug 19 05:25:44 PM PDT 24
Peak memory 198088 kb
Host smart-68a566ed-3173-4184-bfb5-fb3d5ba4e71b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346727391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.346727391
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.224590110
Short name T291
Test name
Test status
Simulation time 289416164 ps
CPU time 1.21 seconds
Started Aug 19 05:25:37 PM PDT 24
Finished Aug 19 05:25:38 PM PDT 24
Peak memory 195900 kb
Host smart-dfc468c0-cecb-4609-8a3d-4ea6218607ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224590110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.224590110
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2648347412
Short name T172
Test name
Test status
Simulation time 232477838 ps
CPU time 1.45 seconds
Started Aug 19 05:25:38 PM PDT 24
Finished Aug 19 05:25:39 PM PDT 24
Peak memory 198212 kb
Host smart-647521ac-8a17-41d5-9b90-33342b1b988b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648347412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2648347412
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1940317711
Short name T441
Test name
Test status
Simulation time 40689641249 ps
CPU time 232.85 seconds
Started Aug 19 05:25:39 PM PDT 24
Finished Aug 19 05:29:32 PM PDT 24
Peak memory 198348 kb
Host smart-f45c5bd8-ada5-4cbe-a721-3bc3bc763b3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940317711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1940317711
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3583098601
Short name T30
Test name
Test status
Simulation time 8550480339 ps
CPU time 75.09 seconds
Started Aug 19 05:25:42 PM PDT 24
Finished Aug 19 05:26:57 PM PDT 24
Peak memory 198568 kb
Host smart-0882eec2-7e2d-4a6a-bfe4-e1eff7057de1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3583098601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3583098601
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.354668752
Short name T317
Test name
Test status
Simulation time 18407563 ps
CPU time 0.57 seconds
Started Aug 19 05:22:47 PM PDT 24
Finished Aug 19 05:22:47 PM PDT 24
Peak memory 194100 kb
Host smart-9cf88b4e-b897-480a-a314-d9c0ead99d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354668752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.354668752
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2379784218
Short name T12
Test name
Test status
Simulation time 53494808 ps
CPU time 0.95 seconds
Started Aug 19 05:22:47 PM PDT 24
Finished Aug 19 05:22:48 PM PDT 24
Peak memory 197428 kb
Host smart-f02f26e9-ab11-4d4d-9f56-dc7864d6ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379784218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2379784218
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.926862007
Short name T422
Test name
Test status
Simulation time 785484866 ps
CPU time 11.15 seconds
Started Aug 19 05:22:41 PM PDT 24
Finished Aug 19 05:22:52 PM PDT 24
Peak memory 197056 kb
Host smart-6908a3cf-c37c-4684-966b-d0a2292d7a68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926862007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.926862007
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4178759111
Short name T701
Test name
Test status
Simulation time 43409135 ps
CPU time 0.75 seconds
Started Aug 19 05:22:43 PM PDT 24
Finished Aug 19 05:22:44 PM PDT 24
Peak memory 194848 kb
Host smart-39a3a829-5fe0-42b7-b584-c96a5b37e8a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178759111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4178759111
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1241903500
Short name T712
Test name
Test status
Simulation time 32724481 ps
CPU time 1.06 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 196012 kb
Host smart-0d83aaaa-a42d-44f5-a556-f927c3d3c961
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241903500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1241903500
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.160309421
Short name T644
Test name
Test status
Simulation time 186549057 ps
CPU time 2.29 seconds
Started Aug 19 05:22:43 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 198216 kb
Host smart-b515da09-df98-4407-a5d6-abe746bf9e5d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160309421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.160309421
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2715712460
Short name T147
Test name
Test status
Simulation time 40703155 ps
CPU time 1.16 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 196472 kb
Host smart-5f64d88b-e586-49cd-908c-283e39fc7384
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715712460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2715712460
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2458345508
Short name T181
Test name
Test status
Simulation time 53225258 ps
CPU time 1.12 seconds
Started Aug 19 05:22:45 PM PDT 24
Finished Aug 19 05:22:47 PM PDT 24
Peak memory 196104 kb
Host smart-22d698f6-29d3-4e8c-941e-d4d2c237e743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458345508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2458345508
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2096540819
Short name T283
Test name
Test status
Simulation time 51977032 ps
CPU time 0.64 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 194488 kb
Host smart-86daffe0-134d-488d-af0b-3e5e380a4610
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096540819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2096540819
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2121482839
Short name T337
Test name
Test status
Simulation time 483086851 ps
CPU time 5.65 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:49 PM PDT 24
Peak memory 198208 kb
Host smart-288dd31e-5b8c-4f70-a9f2-a0a120695495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121482839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2121482839
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.256990610
Short name T263
Test name
Test status
Simulation time 376505121 ps
CPU time 1.03 seconds
Started Aug 19 05:22:43 PM PDT 24
Finished Aug 19 05:22:44 PM PDT 24
Peak memory 196588 kb
Host smart-befc1aa7-fd9e-4526-9e0e-3097c32e9563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256990610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.256990610
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2522993877
Short name T53
Test name
Test status
Simulation time 63097266 ps
CPU time 0.87 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 195544 kb
Host smart-1df0a387-96f3-42e3-947e-4d823a3320b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522993877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2522993877
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3135594419
Short name T574
Test name
Test status
Simulation time 5846241255 ps
CPU time 157.18 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:25:22 PM PDT 24
Peak memory 198356 kb
Host smart-aa6f9a14-6bdc-450e-9ca1-941d996bbb89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135594419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3135594419
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.709743327
Short name T57
Test name
Test status
Simulation time 99714665 ps
CPU time 0.59 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:22:57 PM PDT 24
Peak memory 194820 kb
Host smart-16529e94-74b6-4ccc-b830-bcfea4e6dd8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709743327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.709743327
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3966955016
Short name T450
Test name
Test status
Simulation time 256126639 ps
CPU time 0.78 seconds
Started Aug 19 05:22:46 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 196104 kb
Host smart-f9dde631-0a31-4646-be69-559c7f6b10b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966955016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3966955016
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.598072351
Short name T50
Test name
Test status
Simulation time 820132567 ps
CPU time 3.73 seconds
Started Aug 19 05:22:46 PM PDT 24
Finished Aug 19 05:22:50 PM PDT 24
Peak memory 196480 kb
Host smart-0da5127a-07ee-485e-af44-612e76441ff1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598072351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.598072351
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.223063521
Short name T145
Test name
Test status
Simulation time 189598377 ps
CPU time 0.78 seconds
Started Aug 19 05:22:58 PM PDT 24
Finished Aug 19 05:22:59 PM PDT 24
Peak memory 195972 kb
Host smart-bb99ad02-70e2-4a74-ad11-4f9c7500e913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223063521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.223063521
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4224665057
Short name T559
Test name
Test status
Simulation time 36763679 ps
CPU time 1.06 seconds
Started Aug 19 05:22:45 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 196356 kb
Host smart-3c471519-d595-404e-91ce-cbc537dfb023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224665057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4224665057
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1889529645
Short name T349
Test name
Test status
Simulation time 412303978 ps
CPU time 3.58 seconds
Started Aug 19 05:22:42 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 196428 kb
Host smart-92402a23-2729-40d8-86b6-6dd3669b93cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889529645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1889529645
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1748056973
Short name T583
Test name
Test status
Simulation time 53164785 ps
CPU time 1.47 seconds
Started Aug 19 05:22:44 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 196136 kb
Host smart-e12c9ae8-67b3-4e23-a2ad-26a029df07a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748056973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1748056973
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3317301521
Short name T378
Test name
Test status
Simulation time 260127320 ps
CPU time 1.28 seconds
Started Aug 19 05:22:43 PM PDT 24
Finished Aug 19 05:22:45 PM PDT 24
Peak memory 196248 kb
Host smart-4dc286aa-abdb-4063-a50d-2b69e0df5ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317301521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3317301521
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2035379499
Short name T246
Test name
Test status
Simulation time 93118942 ps
CPU time 0.95 seconds
Started Aug 19 05:22:45 PM PDT 24
Finished Aug 19 05:22:46 PM PDT 24
Peak memory 196116 kb
Host smart-e713e79c-c02f-4372-942c-f8eb09c6a7e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035379499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2035379499
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1581961206
Short name T124
Test name
Test status
Simulation time 1254675523 ps
CPU time 3.16 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:22:59 PM PDT 24
Peak memory 198068 kb
Host smart-5a836a31-939a-4d6b-9813-7c1293d36354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581961206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1581961206
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.4108883826
Short name T179
Test name
Test status
Simulation time 72394831 ps
CPU time 1.41 seconds
Started Aug 19 05:22:47 PM PDT 24
Finished Aug 19 05:22:48 PM PDT 24
Peak memory 195728 kb
Host smart-59371632-dffc-43d5-b816-2fc8aa28f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108883826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.4108883826
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2176690387
Short name T560
Test name
Test status
Simulation time 55087282 ps
CPU time 1.1 seconds
Started Aug 19 05:22:43 PM PDT 24
Finished Aug 19 05:22:44 PM PDT 24
Peak memory 195976 kb
Host smart-b461dc67-3052-4de7-b422-62313ad2f84e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176690387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2176690387
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2424979840
Short name T295
Test name
Test status
Simulation time 88798355952 ps
CPU time 229.57 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:26:46 PM PDT 24
Peak memory 198352 kb
Host smart-48d49c34-d81f-4000-ad11-cf45b6289f4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424979840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2424979840
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1276205312
Short name T59
Test name
Test status
Simulation time 3048762861 ps
CPU time 55.46 seconds
Started Aug 19 05:22:55 PM PDT 24
Finished Aug 19 05:23:51 PM PDT 24
Peak memory 198556 kb
Host smart-d56abad6-0c6a-49aa-8d51-b681685c0ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1276205312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1276205312
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.205043890
Short name T301
Test name
Test status
Simulation time 25764124 ps
CPU time 0.55 seconds
Started Aug 19 05:22:55 PM PDT 24
Finished Aug 19 05:22:56 PM PDT 24
Peak memory 194812 kb
Host smart-56b923ec-d899-4210-ad33-9ddd70c2854b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205043890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.205043890
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1725763158
Short name T163
Test name
Test status
Simulation time 33076252 ps
CPU time 0.86 seconds
Started Aug 19 05:22:53 PM PDT 24
Finished Aug 19 05:22:54 PM PDT 24
Peak memory 195528 kb
Host smart-7244860f-d272-4721-814a-07a91a467cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725763158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1725763158
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2148758600
Short name T199
Test name
Test status
Simulation time 230393093 ps
CPU time 11.97 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:23:08 PM PDT 24
Peak memory 195708 kb
Host smart-c96dfc62-e594-458b-9aaa-52f3bf3696a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148758600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2148758600
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.833032927
Short name T341
Test name
Test status
Simulation time 23174744 ps
CPU time 0.63 seconds
Started Aug 19 05:22:53 PM PDT 24
Finished Aug 19 05:22:54 PM PDT 24
Peak memory 194596 kb
Host smart-6f7683d6-11e3-4549-9b5a-0c4543e78cd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833032927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.833032927
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2776691039
Short name T198
Test name
Test status
Simulation time 107556201 ps
CPU time 1.32 seconds
Started Aug 19 05:22:54 PM PDT 24
Finished Aug 19 05:22:55 PM PDT 24
Peak memory 196968 kb
Host smart-7b3b09e6-d775-4821-acf2-0e6bdff787fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776691039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2776691039
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1147833833
Short name T327
Test name
Test status
Simulation time 54050027 ps
CPU time 2.28 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:22:58 PM PDT 24
Peak memory 198160 kb
Host smart-cad60df5-4451-4398-b592-43fd9364833b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147833833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1147833833
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1759890017
Short name T451
Test name
Test status
Simulation time 181566984 ps
CPU time 1.77 seconds
Started Aug 19 05:22:58 PM PDT 24
Finished Aug 19 05:23:00 PM PDT 24
Peak memory 196272 kb
Host smart-1602becc-9535-43fb-8b94-dbc9155600b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759890017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1759890017
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4148410165
Short name T14
Test name
Test status
Simulation time 126224599 ps
CPU time 1.36 seconds
Started Aug 19 05:22:55 PM PDT 24
Finished Aug 19 05:22:56 PM PDT 24
Peak memory 196072 kb
Host smart-2ff568af-6dcc-4e8f-817d-4c506c4013d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148410165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4148410165
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2826586331
Short name T138
Test name
Test status
Simulation time 405737248 ps
CPU time 1.37 seconds
Started Aug 19 05:22:55 PM PDT 24
Finished Aug 19 05:22:56 PM PDT 24
Peak memory 198268 kb
Host smart-f60cbc1c-9acd-4c4e-b106-29d645b13bf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826586331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2826586331
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3778615602
Short name T129
Test name
Test status
Simulation time 407651208 ps
CPU time 4.34 seconds
Started Aug 19 05:22:53 PM PDT 24
Finished Aug 19 05:22:57 PM PDT 24
Peak memory 198108 kb
Host smart-69b43000-fe55-4cef-a464-23a89c2ca909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778615602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3778615602
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1724366213
Short name T242
Test name
Test status
Simulation time 149845018 ps
CPU time 1.18 seconds
Started Aug 19 05:22:58 PM PDT 24
Finished Aug 19 05:23:00 PM PDT 24
Peak memory 195752 kb
Host smart-a955f198-7bfd-4691-9f13-40696d784a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724366213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1724366213
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2686691754
Short name T211
Test name
Test status
Simulation time 84435044 ps
CPU time 1.44 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:22:57 PM PDT 24
Peak memory 196952 kb
Host smart-8cf8dee9-def7-475c-8390-3bdd448a0359
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686691754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2686691754
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3419336924
Short name T336
Test name
Test status
Simulation time 4089536419 ps
CPU time 109.66 seconds
Started Aug 19 05:22:53 PM PDT 24
Finished Aug 19 05:24:43 PM PDT 24
Peak memory 198404 kb
Host smart-6bbe18f5-a44e-4c30-8377-9eab916aa152
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419336924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3419336924
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4081667221
Short name T309
Test name
Test status
Simulation time 11878994 ps
CPU time 0.6 seconds
Started Aug 19 05:23:03 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 194064 kb
Host smart-cba21100-0a28-4f08-9840-160708dc14d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081667221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4081667221
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2361634528
Short name T457
Test name
Test status
Simulation time 76172501 ps
CPU time 0.68 seconds
Started Aug 19 05:22:54 PM PDT 24
Finished Aug 19 05:22:55 PM PDT 24
Peak memory 194192 kb
Host smart-762559da-eed5-43f8-922e-51811ec57bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361634528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2361634528
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3638045948
Short name T409
Test name
Test status
Simulation time 400152059 ps
CPU time 14.89 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:17 PM PDT 24
Peak memory 198220 kb
Host smart-6dec95e5-bc0b-46ad-8cb4-fe27b37d2c5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638045948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3638045948
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3156452871
Short name T666
Test name
Test status
Simulation time 77171027 ps
CPU time 1.07 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:03 PM PDT 24
Peak memory 196868 kb
Host smart-7af1fc7e-c359-4af9-ac90-426332d705a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156452871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3156452871
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1868900365
Short name T143
Test name
Test status
Simulation time 29643441 ps
CPU time 0.7 seconds
Started Aug 19 05:22:54 PM PDT 24
Finished Aug 19 05:22:55 PM PDT 24
Peak memory 195216 kb
Host smart-be2b1239-db90-4661-a4fe-e46d55e3437e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868900365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1868900365
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2944104562
Short name T699
Test name
Test status
Simulation time 25951828 ps
CPU time 1.08 seconds
Started Aug 19 05:22:54 PM PDT 24
Finished Aug 19 05:22:55 PM PDT 24
Peak memory 196172 kb
Host smart-bbcd4dcc-b4c4-4c27-bbb3-3e10ffcf0036
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944104562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2944104562
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1264663918
Short name T132
Test name
Test status
Simulation time 49581742 ps
CPU time 1.21 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:22:57 PM PDT 24
Peak memory 195904 kb
Host smart-27c7b9ed-0e32-4f4f-ba83-0d58aeedc812
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264663918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1264663918
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3888707973
Short name T279
Test name
Test status
Simulation time 89843235 ps
CPU time 0.93 seconds
Started Aug 19 05:22:55 PM PDT 24
Finished Aug 19 05:22:56 PM PDT 24
Peak memory 196768 kb
Host smart-3713491b-1626-46a8-a18e-0cd5f3fd1916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888707973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3888707973
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3058305649
Short name T258
Test name
Test status
Simulation time 116971721 ps
CPU time 1.13 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:22:57 PM PDT 24
Peak memory 195984 kb
Host smart-f6c31d55-2701-4229-a006-097241c37394
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058305649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3058305649
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.581655298
Short name T156
Test name
Test status
Simulation time 474723620 ps
CPU time 5.76 seconds
Started Aug 19 05:23:03 PM PDT 24
Finished Aug 19 05:23:08 PM PDT 24
Peak memory 197320 kb
Host smart-4334a47c-9cf2-46b0-9d77-2842934e7351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581655298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.581655298
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1622059726
Short name T662
Test name
Test status
Simulation time 211276228 ps
CPU time 1.4 seconds
Started Aug 19 05:22:54 PM PDT 24
Finished Aug 19 05:22:56 PM PDT 24
Peak memory 196972 kb
Host smart-2400055d-0a66-4ef8-b4d7-61e69890402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622059726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1622059726
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3734451752
Short name T607
Test name
Test status
Simulation time 164991690 ps
CPU time 1.01 seconds
Started Aug 19 05:22:56 PM PDT 24
Finished Aug 19 05:22:57 PM PDT 24
Peak memory 196564 kb
Host smart-afbbafdb-ee42-47f2-aaed-50a5e4044ceb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734451752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3734451752
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2636599675
Short name T274
Test name
Test status
Simulation time 6388109167 ps
CPU time 46.77 seconds
Started Aug 19 05:23:04 PM PDT 24
Finished Aug 19 05:23:51 PM PDT 24
Peak memory 192212 kb
Host smart-79391343-5ac5-45ce-af66-abca38d5dfbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636599675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2636599675
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.509422770
Short name T502
Test name
Test status
Simulation time 10427929580 ps
CPU time 17.52 seconds
Started Aug 19 05:23:03 PM PDT 24
Finished Aug 19 05:23:21 PM PDT 24
Peak memory 198548 kb
Host smart-4093d6f6-4dab-49e4-a449-841ec1607db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=509422770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.509422770
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3375594579
Short name T255
Test name
Test status
Simulation time 30335001 ps
CPU time 0.59 seconds
Started Aug 19 05:23:04 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 194772 kb
Host smart-1976b79c-5e71-4849-b663-033757a9963f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375594579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3375594579
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2912008563
Short name T352
Test name
Test status
Simulation time 126288371 ps
CPU time 0.91 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:03 PM PDT 24
Peak memory 195584 kb
Host smart-35aa4590-7958-4817-b10e-0f6083a41efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912008563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2912008563
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1486552719
Short name T174
Test name
Test status
Simulation time 2265208517 ps
CPU time 17.06 seconds
Started Aug 19 05:23:01 PM PDT 24
Finished Aug 19 05:23:18 PM PDT 24
Peak memory 198316 kb
Host smart-090bc5df-ab5b-42be-b457-86d87d6f5608
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486552719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1486552719
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2487115538
Short name T685
Test name
Test status
Simulation time 134712745 ps
CPU time 0.81 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:03 PM PDT 24
Peak memory 195588 kb
Host smart-756999b7-30cf-49a3-91a0-90d627f67755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487115538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2487115538
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3996820460
Short name T531
Test name
Test status
Simulation time 16500787 ps
CPU time 0.67 seconds
Started Aug 19 05:23:05 PM PDT 24
Finished Aug 19 05:23:06 PM PDT 24
Peak memory 194488 kb
Host smart-ea3c238e-c97c-4f5d-baac-6f4b499dfc9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996820460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3996820460
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3721577688
Short name T545
Test name
Test status
Simulation time 223116931 ps
CPU time 2.3 seconds
Started Aug 19 05:23:01 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 196464 kb
Host smart-c0b967f0-007e-4665-b3a2-e1e8e61f666d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721577688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3721577688
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1495897513
Short name T588
Test name
Test status
Simulation time 183097507 ps
CPU time 1.41 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 196676 kb
Host smart-1fd37bda-d258-4567-8368-859ec6e36c65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495897513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1495897513
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2457738003
Short name T616
Test name
Test status
Simulation time 54374124 ps
CPU time 1.22 seconds
Started Aug 19 05:23:03 PM PDT 24
Finished Aug 19 05:23:05 PM PDT 24
Peak memory 197252 kb
Host smart-d15c2591-6317-42ba-9c25-e2a408b0ec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457738003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2457738003
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1659530692
Short name T508
Test name
Test status
Simulation time 68634024 ps
CPU time 1.42 seconds
Started Aug 19 05:23:03 PM PDT 24
Finished Aug 19 05:23:04 PM PDT 24
Peak memory 196780 kb
Host smart-eb63349a-7923-417e-8a5a-d7b17962e42e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659530692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1659530692
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1991962478
Short name T22
Test name
Test status
Simulation time 410214291 ps
CPU time 4.8 seconds
Started Aug 19 05:23:05 PM PDT 24
Finished Aug 19 05:23:10 PM PDT 24
Peak memory 198188 kb
Host smart-909c4433-cb32-48cb-9fc8-bf113bd25e3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991962478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1991962478
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.667069224
Short name T401
Test name
Test status
Simulation time 38038021 ps
CPU time 1.07 seconds
Started Aug 19 05:23:02 PM PDT 24
Finished Aug 19 05:23:03 PM PDT 24
Peak memory 195904 kb
Host smart-5bd01b5b-9309-4150-86ba-817501ee7448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667069224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.667069224
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1785737602
Short name T261
Test name
Test status
Simulation time 94867562 ps
CPU time 1.37 seconds
Started Aug 19 05:23:01 PM PDT 24
Finished Aug 19 05:23:03 PM PDT 24
Peak memory 195684 kb
Host smart-d97fd412-116b-413d-bfed-f8dc16793199
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785737602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1785737602
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1786275565
Short name T260
Test name
Test status
Simulation time 4579186274 ps
CPU time 108.56 seconds
Started Aug 19 05:23:01 PM PDT 24
Finished Aug 19 05:24:50 PM PDT 24
Peak memory 198376 kb
Host smart-f06a7c37-3b33-4f24-9d7f-4762d5cfbd2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786275565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1786275565
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1107006100
Short name T62
Test name
Test status
Simulation time 8191917045 ps
CPU time 312.5 seconds
Started Aug 19 05:23:03 PM PDT 24
Finished Aug 19 05:28:16 PM PDT 24
Peak memory 198536 kb
Host smart-6955ef6a-6645-426d-93c8-3f4fcf25b315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1107006100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1107006100
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2580049028
Short name T889
Test name
Test status
Simulation time 71456637 ps
CPU time 0.74 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 195576 kb
Host smart-1cc30921-85d2-4920-a793-f1f71f8f74cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2580049028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2580049028
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.389864328
Short name T862
Test name
Test status
Simulation time 29594712 ps
CPU time 0.83 seconds
Started Aug 19 04:30:10 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 191036 kb
Host smart-f309f6d3-d538-4b2b-ab88-d0ad37021a2c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389864328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.389864328
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.145972599
Short name T903
Test name
Test status
Simulation time 27197889 ps
CPU time 0.76 seconds
Started Aug 19 04:30:01 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 195696 kb
Host smart-a9e98fb7-7b34-4639-afdd-2451296f7375
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=145972599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.145972599
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1776653804
Short name T891
Test name
Test status
Simulation time 1154440254 ps
CPU time 1.24 seconds
Started Aug 19 04:30:29 PM PDT 24
Finished Aug 19 04:30:31 PM PDT 24
Peak memory 191248 kb
Host smart-6d445a90-6175-4b0a-b1a6-656c12d671ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776653804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1776653804
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.471795139
Short name T923
Test name
Test status
Simulation time 65969547 ps
CPU time 0.81 seconds
Started Aug 19 04:30:24 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 191104 kb
Host smart-ec56757d-0474-4119-902b-ddf794183e2f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=471795139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.471795139
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.720932794
Short name T921
Test name
Test status
Simulation time 43135196 ps
CPU time 0.99 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 191192 kb
Host smart-e6a59081-76c5-4a57-b122-a6cb958bc3d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720932794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.720932794
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1928342456
Short name T856
Test name
Test status
Simulation time 256071824 ps
CPU time 1.24 seconds
Started Aug 19 04:30:18 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 197724 kb
Host smart-cce30a49-2560-4da9-97b7-92b934e4e19a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1928342456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1928342456
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2063988187
Short name T917
Test name
Test status
Simulation time 266723956 ps
CPU time 0.86 seconds
Started Aug 19 04:30:18 PM PDT 24
Finished Aug 19 04:30:19 PM PDT 24
Peak memory 195916 kb
Host smart-893e7dc1-8c14-434f-9cfc-e18a60de082d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063988187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2063988187
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1025235224
Short name T940
Test name
Test status
Simulation time 86768120 ps
CPU time 0.75 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 195672 kb
Host smart-cff10df4-47a5-4d01-a468-0dc84e4ee000
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1025235224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1025235224
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2672957753
Short name T896
Test name
Test status
Simulation time 154753963 ps
CPU time 0.92 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 191200 kb
Host smart-75a023da-8981-453a-bcb4-65f3a66e9e25
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672957753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2672957753
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1040477323
Short name T913
Test name
Test status
Simulation time 299740902 ps
CPU time 1.26 seconds
Started Aug 19 04:30:15 PM PDT 24
Finished Aug 19 04:30:16 PM PDT 24
Peak memory 191228 kb
Host smart-a8762f38-91dc-48d8-9c92-70dfedd2f85b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1040477323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1040477323
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.726160838
Short name T887
Test name
Test status
Simulation time 29455925 ps
CPU time 0.99 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 197088 kb
Host smart-c3cd00f9-ba71-4217-889a-34ed9482af8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726160838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.726160838
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1511409273
Short name T890
Test name
Test status
Simulation time 255639590 ps
CPU time 1.2 seconds
Started Aug 19 04:30:08 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 197556 kb
Host smart-4920f252-ef62-4d6a-ad43-c9eac6488fed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1511409273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1511409273
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2500892485
Short name T919
Test name
Test status
Simulation time 361905229 ps
CPU time 1.01 seconds
Started Aug 19 04:30:15 PM PDT 24
Finished Aug 19 04:30:16 PM PDT 24
Peak memory 197652 kb
Host smart-06cb6cb8-0110-4937-9bfd-0c3bb8d7db54
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500892485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2500892485
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.274720361
Short name T915
Test name
Test status
Simulation time 43423703 ps
CPU time 0.95 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 191340 kb
Host smart-ee05374c-064f-4153-8f51-17f57e72e38c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=274720361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.274720361
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2334512111
Short name T925
Test name
Test status
Simulation time 48063709 ps
CPU time 1.07 seconds
Started Aug 19 04:30:31 PM PDT 24
Finished Aug 19 04:30:33 PM PDT 24
Peak memory 191332 kb
Host smart-4bf605d8-0663-4047-b649-f11d3252a198
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334512111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2334512111
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1077003682
Short name T910
Test name
Test status
Simulation time 56654661 ps
CPU time 1.12 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 197564 kb
Host smart-9ed675ad-6788-489e-842e-4de659fb58b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1077003682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1077003682
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1928877154
Short name T944
Test name
Test status
Simulation time 636347232 ps
CPU time 1.18 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 191320 kb
Host smart-133a76ee-68fa-4294-b3db-6da1b8651750
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928877154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1928877154
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2419704969
Short name T855
Test name
Test status
Simulation time 54791922 ps
CPU time 0.78 seconds
Started Aug 19 04:30:14 PM PDT 24
Finished Aug 19 04:30:15 PM PDT 24
Peak memory 191128 kb
Host smart-d16e7e16-8a07-4dbd-9e51-7703eb0af312
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2419704969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2419704969
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.872814564
Short name T936
Test name
Test status
Simulation time 177499999 ps
CPU time 1.29 seconds
Started Aug 19 04:30:01 PM PDT 24
Finished Aug 19 04:30:03 PM PDT 24
Peak memory 191236 kb
Host smart-8531a8cb-9f9e-4b52-b916-2e22bd0aea02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872814564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.872814564
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2715711297
Short name T922
Test name
Test status
Simulation time 35570364 ps
CPU time 0.98 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 196008 kb
Host smart-e5de6ba1-e5d7-4f63-8ccc-3efa5e7e4bca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2715711297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2715711297
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3435383815
Short name T941
Test name
Test status
Simulation time 135899266 ps
CPU time 0.88 seconds
Started Aug 19 04:29:55 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 191128 kb
Host smart-31e7a3a6-0366-4546-9978-0fa4b4f3e065
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435383815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3435383815
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.529926664
Short name T846
Test name
Test status
Simulation time 238958341 ps
CPU time 1.1 seconds
Started Aug 19 04:30:20 PM PDT 24
Finished Aug 19 04:30:22 PM PDT 24
Peak memory 197680 kb
Host smart-d6d88e9e-c605-4d7f-ba21-f52506b3a0d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=529926664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.529926664
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3340373289
Short name T899
Test name
Test status
Simulation time 310711696 ps
CPU time 0.76 seconds
Started Aug 19 04:30:11 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 191124 kb
Host smart-a3baa389-e348-4160-b3fd-2912065c6fe3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340373289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3340373289
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1725705856
Short name T905
Test name
Test status
Simulation time 59243408 ps
CPU time 1.14 seconds
Started Aug 19 04:30:14 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 196260 kb
Host smart-911a0953-9272-4ec5-a659-d7bfa7250f69
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1725705856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1725705856
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1447102069
Short name T943
Test name
Test status
Simulation time 85455638 ps
CPU time 1.47 seconds
Started Aug 19 04:30:33 PM PDT 24
Finished Aug 19 04:30:34 PM PDT 24
Peak memory 191244 kb
Host smart-eb628994-66a6-429b-b876-78f47e4e56b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447102069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1447102069
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1258610263
Short name T876
Test name
Test status
Simulation time 157570811 ps
CPU time 1.2 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 191332 kb
Host smart-af0a4b9d-55aa-4cb5-9ea9-c42dd1f67282
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1258610263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1258610263
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1455446000
Short name T918
Test name
Test status
Simulation time 166737729 ps
CPU time 0.88 seconds
Started Aug 19 04:29:57 PM PDT 24
Finished Aug 19 04:29:58 PM PDT 24
Peak memory 191044 kb
Host smart-eafe394a-4c07-4f87-a7a1-a1ebe880c706
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455446000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1455446000
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1594314306
Short name T870
Test name
Test status
Simulation time 126653809 ps
CPU time 1 seconds
Started Aug 19 04:30:23 PM PDT 24
Finished Aug 19 04:30:24 PM PDT 24
Peak memory 191304 kb
Host smart-48c44529-a51b-410b-ac6e-4e0041566a78
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1594314306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1594314306
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458882146
Short name T857
Test name
Test status
Simulation time 48669017 ps
CPU time 0.9 seconds
Started Aug 19 04:30:12 PM PDT 24
Finished Aug 19 04:30:13 PM PDT 24
Peak memory 191020 kb
Host smart-04ee9a44-1730-49b4-a24a-965bbfedf19d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458882146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2458882146
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1358543270
Short name T854
Test name
Test status
Simulation time 186959905 ps
CPU time 1.03 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 191336 kb
Host smart-f36cec04-3f0c-4ca2-9958-1c6021e17f5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1358543270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1358543270
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.889950481
Short name T850
Test name
Test status
Simulation time 38630877 ps
CPU time 0.97 seconds
Started Aug 19 04:30:24 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 191240 kb
Host smart-c3f432f9-24c3-441e-9597-8de0a787dc29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889950481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.889950481
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1232124427
Short name T875
Test name
Test status
Simulation time 102394134 ps
CPU time 1.15 seconds
Started Aug 19 04:30:14 PM PDT 24
Finished Aug 19 04:30:15 PM PDT 24
Peak memory 191260 kb
Host smart-fb1b9eda-e482-4392-b6dd-089356894c99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1232124427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1232124427
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3735468898
Short name T911
Test name
Test status
Simulation time 39194085 ps
CPU time 1.24 seconds
Started Aug 19 04:30:27 PM PDT 24
Finished Aug 19 04:30:28 PM PDT 24
Peak memory 191240 kb
Host smart-26ae140a-8f15-4b07-becd-7add8dd48008
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735468898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3735468898
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3295334066
Short name T897
Test name
Test status
Simulation time 193823233 ps
CPU time 0.98 seconds
Started Aug 19 04:30:13 PM PDT 24
Finished Aug 19 04:30:14 PM PDT 24
Peak memory 191324 kb
Host smart-c5af97af-6e4a-46fe-9e94-a228d7d5273a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3295334066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3295334066
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.890883197
Short name T878
Test name
Test status
Simulation time 263123524 ps
CPU time 0.96 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:00 PM PDT 24
Peak memory 191252 kb
Host smart-0c0c42b8-d151-4fee-99f5-f5049750c5cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890883197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.890883197
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2839639061
Short name T901
Test name
Test status
Simulation time 87104434 ps
CPU time 1.41 seconds
Started Aug 19 04:30:13 PM PDT 24
Finished Aug 19 04:30:14 PM PDT 24
Peak memory 197624 kb
Host smart-688f608c-df0b-42f8-b68c-4b90aa540c32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2839639061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2839639061
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3560019476
Short name T933
Test name
Test status
Simulation time 101032706 ps
CPU time 1.41 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 191196 kb
Host smart-7925046c-a24a-45e0-a985-a4d7408b8dc4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560019476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3560019476
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1943222276
Short name T924
Test name
Test status
Simulation time 168550503 ps
CPU time 0.98 seconds
Started Aug 19 04:30:19 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 191216 kb
Host smart-70f277ad-337a-4c8c-bd02-34312d698382
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1943222276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1943222276
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1361582959
Short name T930
Test name
Test status
Simulation time 66488421 ps
CPU time 0.64 seconds
Started Aug 19 04:30:24 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 191040 kb
Host smart-631811d2-d1cd-4c29-9ccf-b247c9feaf52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361582959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1361582959
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2671942572
Short name T939
Test name
Test status
Simulation time 43747525 ps
CPU time 1.23 seconds
Started Aug 19 04:30:17 PM PDT 24
Finished Aug 19 04:30:18 PM PDT 24
Peak memory 196896 kb
Host smart-f5d26f7d-80fa-4f2c-93a4-89d9dc29d842
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2671942572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2671942572
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2800048571
Short name T847
Test name
Test status
Simulation time 95817082 ps
CPU time 1.05 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 197228 kb
Host smart-33fdf372-8e03-40ed-b769-2cdece96c7f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800048571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2800048571
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4102605807
Short name T883
Test name
Test status
Simulation time 70705494 ps
CPU time 1.24 seconds
Started Aug 19 04:30:26 PM PDT 24
Finished Aug 19 04:30:27 PM PDT 24
Peak memory 191344 kb
Host smart-72c4563c-3cb3-40b0-b8b5-48acb3be4e1e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4102605807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4102605807
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3395301080
Short name T849
Test name
Test status
Simulation time 182599694 ps
CPU time 0.98 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 191324 kb
Host smart-dfc4e59d-4300-4680-921c-364d6a5d9124
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395301080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3395301080
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.38794544
Short name T893
Test name
Test status
Simulation time 306378523 ps
CPU time 1.13 seconds
Started Aug 19 04:30:00 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 191268 kb
Host smart-963961b0-974d-4083-86c1-eba4f0f667df
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=38794544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.38794544
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3170869188
Short name T914
Test name
Test status
Simulation time 30513780 ps
CPU time 0.79 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:04 PM PDT 24
Peak memory 191044 kb
Host smart-1a78e850-f684-4593-a527-117220672482
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170869188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3170869188
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1318022226
Short name T902
Test name
Test status
Simulation time 64976445 ps
CPU time 0.95 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 191064 kb
Host smart-d2a7908e-ca8a-44a9-a0e0-ac397d49b4ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1318022226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1318022226
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1821080485
Short name T877
Test name
Test status
Simulation time 220865480 ps
CPU time 1.28 seconds
Started Aug 19 04:30:28 PM PDT 24
Finished Aug 19 04:30:30 PM PDT 24
Peak memory 191272 kb
Host smart-bc7718b0-83f4-4230-8f43-84933db80a10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821080485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1821080485
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2438774115
Short name T935
Test name
Test status
Simulation time 45537598 ps
CPU time 1.22 seconds
Started Aug 19 04:30:14 PM PDT 24
Finished Aug 19 04:30:15 PM PDT 24
Peak memory 191324 kb
Host smart-bb519642-ff0d-40c5-8bd2-ba529e8f8b51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2438774115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2438774115
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.373410114
Short name T871
Test name
Test status
Simulation time 195440028 ps
CPU time 1.4 seconds
Started Aug 19 04:30:28 PM PDT 24
Finished Aug 19 04:30:29 PM PDT 24
Peak memory 197632 kb
Host smart-08ce9598-0054-440f-a3d8-d4bbe70a4bf3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373410114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.373410114
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.877622398
Short name T894
Test name
Test status
Simulation time 49777713 ps
CPU time 1.06 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 191264 kb
Host smart-42a185c2-1955-4a98-a899-317410a0aa46
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=877622398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.877622398
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9477456
Short name T885
Test name
Test status
Simulation time 651501845 ps
CPU time 1.61 seconds
Started Aug 19 04:30:24 PM PDT 24
Finished Aug 19 04:30:26 PM PDT 24
Peak memory 191244 kb
Host smart-640ecc68-768e-44dc-a109-bb709588da01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9477456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.9477456
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2633658536
Short name T884
Test name
Test status
Simulation time 138318351 ps
CPU time 1.35 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 191432 kb
Host smart-3f7061d2-785f-465e-890f-a7a82e276835
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2633658536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2633658536
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1751980926
Short name T895
Test name
Test status
Simulation time 43577038 ps
CPU time 0.73 seconds
Started Aug 19 04:30:03 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 191100 kb
Host smart-e86fe3b1-04e6-4a65-98a9-c1028191ad69
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751980926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1751980926
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2803454931
Short name T942
Test name
Test status
Simulation time 429005762 ps
CPU time 1.11 seconds
Started Aug 19 04:30:25 PM PDT 24
Finished Aug 19 04:30:26 PM PDT 24
Peak memory 191324 kb
Host smart-1fe0a68b-01b8-431b-a1dc-7e339c751e60
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2803454931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2803454931
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1206965648
Short name T867
Test name
Test status
Simulation time 29338767 ps
CPU time 0.83 seconds
Started Aug 19 04:30:17 PM PDT 24
Finished Aug 19 04:30:18 PM PDT 24
Peak memory 191020 kb
Host smart-b93812c3-e051-423b-8df9-c3d772737b86
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206965648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1206965648
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.4234389769
Short name T900
Test name
Test status
Simulation time 183626325 ps
CPU time 1.2 seconds
Started Aug 19 04:30:18 PM PDT 24
Finished Aug 19 04:30:20 PM PDT 24
Peak memory 191252 kb
Host smart-e51dbd94-4816-4618-8581-adebd1f5bbd7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4234389769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.4234389769
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2362956810
Short name T864
Test name
Test status
Simulation time 57908705 ps
CPU time 1.1 seconds
Started Aug 19 04:30:22 PM PDT 24
Finished Aug 19 04:30:24 PM PDT 24
Peak memory 191244 kb
Host smart-61df40bb-de4e-4f1d-a0cf-81af02fd3f28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362956810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2362956810
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1713108532
Short name T853
Test name
Test status
Simulation time 631280255 ps
CPU time 1.25 seconds
Started Aug 19 04:30:26 PM PDT 24
Finished Aug 19 04:30:27 PM PDT 24
Peak memory 191236 kb
Host smart-d9ec76b2-32d2-4963-ba5c-0b55f1aacb6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1713108532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1713108532
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1589974190
Short name T882
Test name
Test status
Simulation time 35740868 ps
CPU time 1.03 seconds
Started Aug 19 04:30:22 PM PDT 24
Finished Aug 19 04:30:23 PM PDT 24
Peak memory 197576 kb
Host smart-15603bef-72c3-4276-b761-3447a2a1a670
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589974190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1589974190
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2228855982
Short name T858
Test name
Test status
Simulation time 735455014 ps
CPU time 1.14 seconds
Started Aug 19 04:30:29 PM PDT 24
Finished Aug 19 04:30:30 PM PDT 24
Peak memory 191248 kb
Host smart-8f1ab026-c772-4c90-8fe8-bcc3d8fd95d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2228855982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2228855982
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1717972761
Short name T869
Test name
Test status
Simulation time 39143254 ps
CPU time 0.89 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 191100 kb
Host smart-1a5f5f8a-e3a3-4315-a6f3-fb2f10d3aa57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717972761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1717972761
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.421845445
Short name T852
Test name
Test status
Simulation time 468437036 ps
CPU time 1.24 seconds
Started Aug 19 04:30:01 PM PDT 24
Finished Aug 19 04:30:02 PM PDT 24
Peak memory 191260 kb
Host smart-180f2e30-6737-4c13-aed4-abc1510b4da3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=421845445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.421845445
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126060006
Short name T874
Test name
Test status
Simulation time 33015934 ps
CPU time 0.92 seconds
Started Aug 19 04:30:21 PM PDT 24
Finished Aug 19 04:30:22 PM PDT 24
Peak memory 191036 kb
Host smart-4922f70e-ad67-4681-83d7-9296dc1891d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126060006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4126060006
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1932103144
Short name T920
Test name
Test status
Simulation time 34961877 ps
CPU time 0.91 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 196528 kb
Host smart-74b9a6b9-0dc3-4fd5-aa40-f163a318db4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1932103144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1932103144
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1481962209
Short name T898
Test name
Test status
Simulation time 173239838 ps
CPU time 0.96 seconds
Started Aug 19 04:30:21 PM PDT 24
Finished Aug 19 04:30:22 PM PDT 24
Peak memory 191312 kb
Host smart-f456623b-737c-465b-a12e-9cbcb6418990
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481962209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1481962209
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3354596670
Short name T929
Test name
Test status
Simulation time 54362609 ps
CPU time 0.73 seconds
Started Aug 19 04:30:11 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 191000 kb
Host smart-2288316e-393b-429b-8f4a-edbbf6b01fda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3354596670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3354596670
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.666468313
Short name T879
Test name
Test status
Simulation time 90056023 ps
CPU time 0.69 seconds
Started Aug 19 04:30:11 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 191124 kb
Host smart-a96fe5e5-0f0a-4e1a-a482-5381ae8b1d2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666468313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.666468313
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.282753447
Short name T881
Test name
Test status
Simulation time 213161588 ps
CPU time 0.69 seconds
Started Aug 19 04:30:08 PM PDT 24
Finished Aug 19 04:30:09 PM PDT 24
Peak memory 194612 kb
Host smart-c99eba9d-f3ff-49e8-bb8c-d7816e893b6c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=282753447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.282753447
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.702868921
Short name T859
Test name
Test status
Simulation time 148032903 ps
CPU time 1.38 seconds
Started Aug 19 04:29:56 PM PDT 24
Finished Aug 19 04:29:57 PM PDT 24
Peak memory 197620 kb
Host smart-e745663d-a68e-46f7-8cfb-88ea741cda72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702868921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.702868921
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2376892835
Short name T861
Test name
Test status
Simulation time 270872329 ps
CPU time 1.32 seconds
Started Aug 19 04:30:11 PM PDT 24
Finished Aug 19 04:30:13 PM PDT 24
Peak memory 191252 kb
Host smart-942ed2a5-65c8-4f80-a343-ec7916fce244
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2376892835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2376892835
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2773911397
Short name T888
Test name
Test status
Simulation time 34986330 ps
CPU time 0.79 seconds
Started Aug 19 04:30:22 PM PDT 24
Finished Aug 19 04:30:23 PM PDT 24
Peak memory 195720 kb
Host smart-58ce0287-73dd-4383-ac9e-feec2e14807d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773911397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2773911397
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.240300719
Short name T904
Test name
Test status
Simulation time 40906493 ps
CPU time 1.33 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 197600 kb
Host smart-b7d0f50a-2018-4ff2-826a-8b541d4bfebb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=240300719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.240300719
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3744132523
Short name T934
Test name
Test status
Simulation time 84623642 ps
CPU time 1.38 seconds
Started Aug 19 04:30:25 PM PDT 24
Finished Aug 19 04:30:26 PM PDT 24
Peak memory 191224 kb
Host smart-17f2a87c-567c-4bfe-a8ed-724e2636a724
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744132523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3744132523
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1653132773
Short name T912
Test name
Test status
Simulation time 26649530 ps
CPU time 0.76 seconds
Started Aug 19 04:30:12 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 191020 kb
Host smart-cc396e3b-f22a-4e0a-bf88-b0b7a9db9b1a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1653132773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1653132773
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1240350103
Short name T865
Test name
Test status
Simulation time 194767335 ps
CPU time 1.28 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 191240 kb
Host smart-6a54c56a-d965-449b-ab57-018cdfd33b67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240350103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1240350103
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.757238595
Short name T938
Test name
Test status
Simulation time 45627267 ps
CPU time 0.97 seconds
Started Aug 19 04:30:27 PM PDT 24
Finished Aug 19 04:30:28 PM PDT 24
Peak memory 191236 kb
Host smart-f33d7231-4568-40a6-9685-978228484088
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=757238595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.757238595
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1331968757
Short name T872
Test name
Test status
Simulation time 63058765 ps
CPU time 1.11 seconds
Started Aug 19 04:30:12 PM PDT 24
Finished Aug 19 04:30:13 PM PDT 24
Peak memory 197572 kb
Host smart-0e241221-a09f-4b58-b720-d68d3825d6ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331968757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1331968757
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2534334362
Short name T892
Test name
Test status
Simulation time 54769658 ps
CPU time 0.72 seconds
Started Aug 19 04:30:04 PM PDT 24
Finished Aug 19 04:30:05 PM PDT 24
Peak memory 191132 kb
Host smart-d4922264-2bb9-4cd4-a97e-cb22e1f11329
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2534334362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2534334362
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2665854859
Short name T908
Test name
Test status
Simulation time 196159142 ps
CPU time 1.34 seconds
Started Aug 19 04:30:24 PM PDT 24
Finished Aug 19 04:30:25 PM PDT 24
Peak memory 191268 kb
Host smart-a8190fb6-825f-4ca1-bd74-b7a615a965b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665854859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2665854859
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4288213673
Short name T928
Test name
Test status
Simulation time 59258631 ps
CPU time 0.67 seconds
Started Aug 19 04:30:25 PM PDT 24
Finished Aug 19 04:30:26 PM PDT 24
Peak memory 191024 kb
Host smart-96e68d3d-7ce5-42e7-95d8-86164ef8cd40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4288213673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4288213673
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3269741351
Short name T907
Test name
Test status
Simulation time 61830053 ps
CPU time 0.81 seconds
Started Aug 19 04:30:26 PM PDT 24
Finished Aug 19 04:30:27 PM PDT 24
Peak memory 195616 kb
Host smart-bde598b0-8734-452d-8f86-c2cb1beb34b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269741351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3269741351
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.304070856
Short name T848
Test name
Test status
Simulation time 53622974 ps
CPU time 0.81 seconds
Started Aug 19 04:30:05 PM PDT 24
Finished Aug 19 04:30:06 PM PDT 24
Peak memory 191148 kb
Host smart-ec9bdc4f-c283-4391-88a3-86215fb7201d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=304070856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.304070856
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.463505712
Short name T880
Test name
Test status
Simulation time 69635044 ps
CPU time 1.19 seconds
Started Aug 19 04:30:25 PM PDT 24
Finished Aug 19 04:30:27 PM PDT 24
Peak memory 197580 kb
Host smart-c345141e-ab3a-48c9-8ec6-90406425daa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463505712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.463505712
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2469101895
Short name T926
Test name
Test status
Simulation time 46883157 ps
CPU time 1.15 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:08 PM PDT 24
Peak memory 191340 kb
Host smart-c9e59eb0-74aa-4c57-8b57-1fe28a519ca6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2469101895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2469101895
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946915953
Short name T931
Test name
Test status
Simulation time 333142363 ps
CPU time 1.06 seconds
Started Aug 19 04:30:26 PM PDT 24
Finished Aug 19 04:30:27 PM PDT 24
Peak memory 196120 kb
Host smart-ee4e55ef-73a1-4700-9092-99d026d07b78
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946915953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3946915953
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4286415540
Short name T873
Test name
Test status
Simulation time 57720674 ps
CPU time 0.81 seconds
Started Aug 19 04:30:07 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 191048 kb
Host smart-b7dbd79a-7eb9-46b7-a9ae-a63e159fa553
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4286415540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4286415540
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4051229795
Short name T937
Test name
Test status
Simulation time 73329929 ps
CPU time 1.22 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 196216 kb
Host smart-f0304d5f-8e46-4648-a0be-68975579998a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051229795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4051229795
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1417182876
Short name T927
Test name
Test status
Simulation time 151238856 ps
CPU time 1.13 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 191252 kb
Host smart-7bf88e51-acc5-4ea3-a84b-ad86760217cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1417182876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1417182876
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4242097135
Short name T932
Test name
Test status
Simulation time 87745991 ps
CPU time 1.25 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 191244 kb
Host smart-85b66aa1-5606-438e-8500-edcfe600950c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242097135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4242097135
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3586580867
Short name T866
Test name
Test status
Simulation time 199403788 ps
CPU time 1.08 seconds
Started Aug 19 04:30:14 PM PDT 24
Finished Aug 19 04:30:16 PM PDT 24
Peak memory 197136 kb
Host smart-669383b0-a21c-41f4-ba05-dde902161bd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3586580867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3586580867
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2265637693
Short name T863
Test name
Test status
Simulation time 628474128 ps
CPU time 1.01 seconds
Started Aug 19 04:30:09 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 191312 kb
Host smart-1b5cfa0d-35c3-4b5e-adb8-829783e58590
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265637693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2265637693
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.639736783
Short name T909
Test name
Test status
Simulation time 64574487 ps
CPU time 1.23 seconds
Started Aug 19 04:30:08 PM PDT 24
Finished Aug 19 04:30:10 PM PDT 24
Peak memory 196896 kb
Host smart-e67b4183-402b-47ea-82a4-c1a862e20dcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=639736783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.639736783
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3890185906
Short name T868
Test name
Test status
Simulation time 50678272 ps
CPU time 1.01 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 191356 kb
Host smart-542f55ab-4c17-473b-b213-ff9751052809
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890185906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3890185906
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2073407630
Short name T945
Test name
Test status
Simulation time 221578033 ps
CPU time 1.08 seconds
Started Aug 19 04:30:10 PM PDT 24
Finished Aug 19 04:30:12 PM PDT 24
Peak memory 191312 kb
Host smart-2b995df0-f83c-410a-8772-ea853029dd6d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2073407630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2073407630
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3822385825
Short name T886
Test name
Test status
Simulation time 312419059 ps
CPU time 1.29 seconds
Started Aug 19 04:30:10 PM PDT 24
Finished Aug 19 04:30:11 PM PDT 24
Peak memory 191316 kb
Host smart-1943a86f-d4c8-4147-b5fe-66b0cd4d1162
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822385825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3822385825
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3548440717
Short name T906
Test name
Test status
Simulation time 166632837 ps
CPU time 1.15 seconds
Started Aug 19 04:30:06 PM PDT 24
Finished Aug 19 04:30:07 PM PDT 24
Peak memory 197668 kb
Host smart-906679f5-037e-4a8f-ae05-3db3af07d1b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3548440717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3548440717
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2345356473
Short name T851
Test name
Test status
Simulation time 138447721 ps
CPU time 1.18 seconds
Started Aug 19 04:30:17 PM PDT 24
Finished Aug 19 04:30:19 PM PDT 24
Peak memory 191332 kb
Host smart-7e9542e4-45a9-4dd8-8e95-b6d643f60e85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345356473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2345356473
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2888154257
Short name T860
Test name
Test status
Simulation time 79795292 ps
CPU time 0.94 seconds
Started Aug 19 04:29:59 PM PDT 24
Finished Aug 19 04:30:01 PM PDT 24
Peak memory 191376 kb
Host smart-ba33b4f7-ae64-4b82-98fc-161a162cea1a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2888154257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2888154257
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.946891750
Short name T916
Test name
Test status
Simulation time 211191626 ps
CPU time 1.08 seconds
Started Aug 19 04:29:54 PM PDT 24
Finished Aug 19 04:29:55 PM PDT 24
Peak memory 191372 kb
Host smart-f08ea0ff-6b82-4ed2-9468-42d8fbedb2ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946891750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.946891750
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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