Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1254158	1			T20	81		T21	1		T22	1
all_pins[1]	1254158	1			T20	81		T21	1		T22	1
all_pins[2]	1254158	1			T20	81		T21	1		T22	1
all_pins[3]	1254158	1			T20	81		T21	1		T22	1
all_pins[4]	1254158	1			T20	81		T21	1		T22	1
all_pins[5]	1254158	1			T20	81		T21	1		T22	1
all_pins[6]	1254158	1			T20	81		T21	1		T22	1
all_pins[7]	1254158	1			T20	81		T21	1		T22	1
all_pins[8]	1254158	1			T20	81		T21	1		T22	1
all_pins[9]	1254158	1			T20	81		T21	1		T22	1
all_pins[10]	1254158	1			T20	81		T21	1		T22	1
all_pins[11]	1254158	1			T20	81		T21	1		T22	1
all_pins[12]	1254158	1			T20	81		T21	1		T22	1
all_pins[13]	1254158	1			T20	81		T21	1		T22	1
all_pins[14]	1254158	1			T20	81		T21	1		T22	1
all_pins[15]	1254158	1			T20	81		T21	1		T22	1
all_pins[16]	1254158	1			T20	81		T21	1		T22	1
all_pins[17]	1254158	1			T20	81		T21	1		T22	1
all_pins[18]	1254158	1			T20	81		T21	1		T22	1
all_pins[19]	1254158	1			T20	81		T21	1		T22	1
all_pins[20]	1254158	1			T20	81		T21	1		T22	1
all_pins[21]	1254158	1			T20	81		T21	1		T22	1
all_pins[22]	1254158	1			T20	81		T21	1		T22	1
all_pins[23]	1254158	1			T20	81		T21	1		T22	1
all_pins[24]	1254158	1			T20	81		T21	1		T22	1
all_pins[25]	1254158	1			T20	81		T21	1		T22	1
all_pins[26]	1254158	1			T20	81		T21	1		T22	1
all_pins[27]	1254158	1			T20	81		T21	1		T22	1
all_pins[28]	1254158	1			T20	81		T21	1		T22	1
all_pins[29]	1254158	1			T20	81		T21	1		T22	1
all_pins[30]	1254158	1			T20	81		T21	1		T22	1
all_pins[31]	1254158	1			T20	81		T21	1		T22	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	24946531	1			T20	2178		T21	32		T22	32
values[0x1]	15186525	1			T20	414		T26	2914		T27	6921
transitions[0x0=>0x1]	9094542	1			T20	287		T26	1766		T27	4230
transitions[0x1=>0x0]	9094385	1			T20	287		T26	1766		T27	4229

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	780606	1			T20	71		T21	1		T22	1
all_pins[0]	values[0x1]	473552	1			T20	10		T26	94		T27	177
all_pins[0]	transitions[0x0=>0x1]	292020	1			T20	8		T26	57		T27	106
all_pins[0]	transitions[0x1=>0x0]	294414	1			T20	2		T26	42		T27	209
all_pins[1]	values[0x0]	780010	1			T20	61		T21	1		T22	1
all_pins[1]	values[0x1]	474148	1			T20	20		T26	82		T27	216
all_pins[1]	transitions[0x0=>0x1]	284668	1			T20	18		T26	56		T27	125
all_pins[1]	transitions[0x1=>0x0]	284072	1			T20	8		T26	68		T27	86
all_pins[2]	values[0x0]	780906	1			T20	74		T21	1		T22	1
all_pins[2]	values[0x1]	473252	1			T20	7		T26	60		T27	134
all_pins[2]	transitions[0x0=>0x1]	284382	1			T20	2		T26	50		T27	95
all_pins[2]	transitions[0x1=>0x0]	285278	1			T20	15		T26	72		T27	177
all_pins[3]	values[0x0]	782155	1			T20	68		T21	1		T22	1
all_pins[3]	values[0x1]	472003	1			T20	13		T26	95		T27	248
all_pins[3]	transitions[0x0=>0x1]	282134	1			T20	13		T26	77		T27	191
all_pins[3]	transitions[0x1=>0x0]	283383	1			T20	7		T26	42		T27	77
all_pins[4]	values[0x0]	780216	1			T20	76		T21	1		T22	1
all_pins[4]	values[0x1]	473942	1			T20	5		T26	94		T27	154
all_pins[4]	transitions[0x0=>0x1]	285172	1			T20	4		T26	67		T27	90
all_pins[4]	transitions[0x1=>0x0]	283233	1			T20	12		T26	68		T27	184
all_pins[5]	values[0x0]	778397	1			T20	68		T21	1		T22	1
all_pins[5]	values[0x1]	475761	1			T20	13		T26	64		T27	206
all_pins[5]	transitions[0x0=>0x1]	283485	1			T20	12		T26	34		T27	140
all_pins[5]	transitions[0x1=>0x0]	281666	1			T20	4		T26	64		T27	88
all_pins[6]	values[0x0]	781001	1			T20	74		T21	1		T22	1
all_pins[6]	values[0x1]	473157	1			T20	7		T26	130		T27	254
all_pins[6]	transitions[0x0=>0x1]	282250	1			T20	4		T26	96		T27	201
all_pins[6]	transitions[0x1=>0x0]	284854	1			T20	10		T26	30		T27	153
all_pins[7]	values[0x0]	774106	1			T20	60		T21	1		T22	1
all_pins[7]	values[0x1]	480052	1			T20	21		T26	96		T27	199
all_pins[7]	transitions[0x0=>0x1]	288840	1			T20	14		T26	43		T27	108
all_pins[7]	transitions[0x1=>0x0]	281945	1			T26	77		T27	163		T1	9
all_pins[8]	values[0x0]	780416	1			T20	67		T21	1		T22	1
all_pins[8]	values[0x1]	473742	1			T20	14		T26	109		T27	186
all_pins[8]	transitions[0x0=>0x1]	281875	1			T20	10		T26	64		T27	111
all_pins[8]	transitions[0x1=>0x0]	288185	1			T20	17		T26	51		T27	124
all_pins[9]	values[0x0]	781726	1			T20	66		T21	1		T22	1
all_pins[9]	values[0x1]	472432	1			T20	15		T26	56		T27	233
all_pins[9]	transitions[0x0=>0x1]	282788	1			T20	10		T26	33		T27	180
all_pins[9]	transitions[0x1=>0x0]	284098	1			T20	9		T26	86		T27	133
all_pins[10]	values[0x0]	781606	1			T20	75		T21	1		T22	1
all_pins[10]	values[0x1]	472552	1			T20	6		T26	84		T27	219
all_pins[10]	transitions[0x0=>0x1]	282675	1			T20	3		T26	71		T27	106
all_pins[10]	transitions[0x1=>0x0]	282555	1			T20	12		T26	43		T27	120
all_pins[11]	values[0x0]	778023	1			T20	64		T21	1		T22	1
all_pins[11]	values[0x1]	476135	1			T20	17		T26	70		T27	215
all_pins[11]	transitions[0x0=>0x1]	285614	1			T20	17		T26	50		T27	126
all_pins[11]	transitions[0x1=>0x0]	282031	1			T20	6		T26	64		T27	130
all_pins[12]	values[0x0]	777517	1			T20	65		T21	1		T22	1
all_pins[12]	values[0x1]	476641	1			T20	16		T26	111		T27	233
all_pins[12]	transitions[0x0=>0x1]	285124	1			T20	12		T26	77		T27	155
all_pins[12]	transitions[0x1=>0x0]	284618	1			T20	13		T26	36		T27	137
all_pins[13]	values[0x0]	778010	1			T20	76		T21	1		T22	1
all_pins[13]	values[0x1]	476148	1			T20	5		T26	126		T27	230
all_pins[13]	transitions[0x0=>0x1]	284252	1			T20	4		T26	59		T27	140
all_pins[13]	transitions[0x1=>0x0]	284745	1			T20	15		T26	44		T27	143
all_pins[14]	values[0x0]	777698	1			T20	68		T21	1		T22	1
all_pins[14]	values[0x1]	476460	1			T20	13		T26	114		T27	233
all_pins[14]	transitions[0x0=>0x1]	284551	1			T20	12		T26	53		T27	134
all_pins[14]	transitions[0x1=>0x0]	284239	1			T20	4		T26	65		T27	131
all_pins[15]	values[0x0]	778789	1			T20	75		T21	1		T22	1
all_pins[15]	values[0x1]	475369	1			T20	6		T26	100		T27	222
all_pins[15]	transitions[0x0=>0x1]	284934	1			T20	6		T26	44		T27	118
all_pins[15]	transitions[0x1=>0x0]	286025	1			T20	13		T26	58		T27	129
all_pins[16]	values[0x0]	781509	1			T20	54		T21	1		T22	1
all_pins[16]	values[0x1]	472649	1			T20	27		T26	124		T27	185
all_pins[16]	transitions[0x0=>0x1]	282827	1			T20	25		T26	73		T27	133
all_pins[16]	transitions[0x1=>0x0]	285547	1			T20	4		T26	49		T27	170
all_pins[17]	values[0x0]	778330	1			T20	63		T21	1		T22	1
all_pins[17]	values[0x1]	475828	1			T20	18		T26	89		T27	152
all_pins[17]	transitions[0x0=>0x1]	285231	1			T20	4		T26	43		T27	107
all_pins[17]	transitions[0x1=>0x0]	282052	1			T20	13		T26	78		T27	140
all_pins[18]	values[0x0]	781016	1			T20	66		T21	1		T22	1
all_pins[18]	values[0x1]	473142	1			T20	15		T26	48		T27	226
all_pins[18]	transitions[0x0=>0x1]	281822	1			T20	7		T26	29		T27	176
all_pins[18]	transitions[0x1=>0x0]	284508	1			T20	10		T26	70		T27	102
all_pins[19]	values[0x0]	780683	1			T20	66		T21	1		T22	1
all_pins[19]	values[0x1]	473475	1			T20	15		T26	50		T27	243
all_pins[19]	transitions[0x0=>0x1]	285506	1			T20	6		T26	34		T27	158
all_pins[19]	transitions[0x1=>0x0]	285173	1			T20	6		T26	32		T27	141
all_pins[20]	values[0x0]	778948	1			T20	67		T21	1		T22	1
all_pins[20]	values[0x1]	475210	1			T20	14		T26	100		T27	280
all_pins[20]	transitions[0x0=>0x1]	285180	1			T20	14		T26	73		T27	159
all_pins[20]	transitions[0x1=>0x0]	283445	1			T20	15		T26	23		T27	122
all_pins[21]	values[0x0]	778605	1			T20	74		T21	1		T22	1
all_pins[21]	values[0x1]	475553	1			T20	7		T26	96		T27	230
all_pins[21]	transitions[0x0=>0x1]	283263	1			T20	1		T26	64		T27	98
all_pins[21]	transitions[0x1=>0x0]	282920	1			T20	8		T26	68		T27	148
all_pins[22]	values[0x0]	780975	1			T20	69		T21	1		T22	1
all_pins[22]	values[0x1]	473183	1			T20	12		T26	101		T27	181
all_pins[22]	transitions[0x0=>0x1]	282904	1			T20	9		T26	56		T27	101
all_pins[22]	transitions[0x1=>0x0]	285274	1			T20	4		T26	51		T27	150
all_pins[23]	values[0x0]	778406	1			T20	74		T21	1		T22	1
all_pins[23]	values[0x1]	475752	1			T20	7		T26	91		T27	266
all_pins[23]	transitions[0x0=>0x1]	285086	1			T20	4		T26	34		T27	157
all_pins[23]	transitions[0x1=>0x0]	282517	1			T20	9		T26	44		T27	72
all_pins[24]	values[0x0]	782261	1			T20	59		T21	1		T22	1
all_pins[24]	values[0x1]	471897	1			T20	22		T26	71		T27	223
all_pins[24]	transitions[0x0=>0x1]	280171	1			T20	20		T26	48		T27	129
all_pins[24]	transitions[0x1=>0x0]	284026	1			T20	5		T26	68		T27	172
all_pins[25]	values[0x0]	779144	1			T20	78		T21	1		T22	1
all_pins[25]	values[0x1]	475014	1			T20	3		T26	99		T27	229
all_pins[25]	transitions[0x0=>0x1]	285641	1			T20	1		T26	77		T27	135
all_pins[25]	transitions[0x1=>0x0]	282524	1			T20	20		T26	49		T27	129
all_pins[26]	values[0x0]	778885	1			T20	56		T21	1		T22	1
all_pins[26]	values[0x1]	475273	1			T20	25		T26	83		T27	176
all_pins[26]	transitions[0x0=>0x1]	284811	1			T20	22		T26	49		T27	66
all_pins[26]	transitions[0x1=>0x0]	284552	1			T26	65		T27	119		T1	6
all_pins[27]	values[0x0]	777603	1			T20	65		T21	1		T22	1
all_pins[27]	values[0x1]	476555	1			T20	16		T26	103		T27	192
all_pins[27]	transitions[0x0=>0x1]	283889	1			T20	5		T26	68		T27	139
all_pins[27]	transitions[0x1=>0x0]	282607	1			T20	14		T26	48		T27	123
all_pins[28]	values[0x0]	783403	1			T20	62		T21	1		T22	1
all_pins[28]	values[0x1]	470755	1			T20	19		T26	103		T27	278
all_pins[28]	transitions[0x0=>0x1]	280143	1			T20	9		T26	36		T27	165
all_pins[28]	transitions[0x1=>0x0]	285943	1			T20	6		T26	36		T27	79
all_pins[29]	values[0x0]	778205	1			T20	69		T21	1		T22	1
all_pins[29]	values[0x1]	475953	1			T20	12		T26	64		T27	226
all_pins[29]	transitions[0x0=>0x1]	285605	1			T20	3		T26	40		T27	92
all_pins[29]	transitions[0x1=>0x0]	280407	1			T20	10		T26	79		T27	144
all_pins[30]	values[0x0]	779321	1			T20	71		T21	1		T22	1
all_pins[30]	values[0x1]	474837	1			T20	10		T26	128		T27	194
all_pins[30]	transitions[0x0=>0x1]	283357	1			T20	6		T26	89		T27	114
all_pins[30]	transitions[0x1=>0x0]	284473	1			T20	8		T26	25		T27	146
all_pins[31]	values[0x0]	778055	1			T20	77		T21	1		T22	1
all_pins[31]	values[0x1]	476103	1			T20	4		T26	79		T27	281
all_pins[31]	transitions[0x0=>0x1]	284342	1			T20	2		T26	22		T27	175
all_pins[31]	transitions[0x1=>0x0]	283076	1			T20	8		T26	71		T27	88