Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[1]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[2]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[3]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[4]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[5]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[6]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[7]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[8]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[9]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[10]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[11]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[12]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[13]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[14]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[15]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[16]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[17]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[18]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[19]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[20]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[21]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[22]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[23]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[24]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[25]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[26]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[27]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[28]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[29]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[30]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[31]	5174808	1			T20	170		T21	167		T22	445

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86683266

1

T20

2396

T21

1180

T22

11287

auto[1]

78910590

1

T20

3044

T21

4164

T22

2953

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138479917

1

T20

5029

T21

5066

T22

10511

auto[1]

27113939

1

T20

411

T21

278

T22

3729

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130729194

1

T20

4148

T21

3162

T22

7734

auto[1]

34864662

1

T20

1292

T21

2182

T22

6506

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	1893032	1			T20	17		T21	19		T22	240
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	1766527	1			T20	80		T21	56		T22	28
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	425312	1			T21	2		T22	32		T23	20
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	393698	1			T20	23		T21	11		T22	103
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	275437	1			T20	37		T21	79		T22	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	420802	1			T20	13		T22	31		T23	17
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	1882011	1			T20	47		T21	10		T22	158
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	1780885	1			T20	71		T21	38		T22	20
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	427652	1			T21	2		T22	50		T23	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	389193	1			T20	27		T21	19		T22	139
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	274048	1			T20	16		T21	90		T22	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	421019	1			T20	9		T21	8		T22	64
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	1888865	1			T20	85		T21	18		T22	176
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	1769685	1			T20	53		T21	64		T22	10
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	425992	1			T20	2		T21	2		T22	55
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	392537	1			T20	17		T21	21		T22	142
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	274757	1			T20	4		T21	54		T22	28
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	422972	1			T20	9		T21	8		T22	34
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	1889108	1			T20	48		T21	21		T22	170
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	1769809	1			T20	83		T21	109		T22	18
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	426959	1			T20	5		T21	6		T22	33
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	391117	1			T20	11		T21	4		T22	145
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	273020	1			T20	15		T21	27		T22	18
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	424795	1			T20	8		T22	61		T23	35
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	1895355	1			T20	67		T21	33		T22	170
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	1761031	1			T20	58		T21	105		T22	17
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	426235	1			T20	3		T21	12		T22	46
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	390636	1			T20	15		T21	1		T22	140
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	277586	1			T20	17		T21	16		T22	20
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	423965	1			T20	10		T22	52		T23	24
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	1882247	1			T20	53		T21	22		T22	159
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	1774351	1			T20	53		T21	76		T22	23
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	424480	1			T21	4		T22	71		T23	20
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	392239	1			T20	31		T21	12		T22	120
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	275274	1			T20	22		T21	45		T22	20
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	426217	1			T20	11		T21	8		T22	52
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	1892108	1			T20	48		T21	16		T22	130
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	1768362	1			T20	80		T21	71		T22	15
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	425278	1			T21	6		T22	63		T23	23
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	391236	1			T20	19		T21	13		T22	170
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	275713	1			T20	14		T21	55		T22	30
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	422111	1			T20	9		T21	6		T22	37
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	1888112	1			T20	35		T21	27		T22	156
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	1770260	1			T20	81		T21	81		T22	31
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	424862	1			T20	16		T21	4		T22	88
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	393886	1			T20	24		T21	6		T22	128
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	275707	1			T20	6		T21	37		T22	17
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	421981	1			T20	8		T21	12		T22	25
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	1889771	1			T20	42		T21	19		T22	171
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	1769427	1			T20	92		T21	65		T22	24
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	425907	1			T20	15		T21	6		T22	84
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	392840	1			T20	17		T21	9		T22	107
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	276123	1			T20	4		T21	66		T22	7
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	420740	1			T21	2		T22	52		T23	14
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	1884544	1			T20	54		T21	18		T22	152
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	1775636	1			T20	59		T21	72		T22	17
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	427739	1			T20	10		T21	2		T22	80
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	390795	1			T20	31		T21	9		T22	148
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	272976	1			T20	14		T21	60		T22	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	423118	1			T20	2		T21	6		T22	30
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	1894950	1			T20	56		T21	15		T22	179
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	1764783	1			T20	40		T21	69		T22	31
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	424949	1			T21	2		T22	68		T23	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	392708	1			T20	34		T21	16		T22	111
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	277565	1			T20	18		T21	57		T22	8
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	419853	1			T20	22		T21	8		T22	48
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	1884193	1			T20	50		T21	16		T22	162
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	1775287	1			T20	72		T21	64		T22	14
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	426399	1			T20	2		T21	2		T22	59
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	391033	1			T20	12		T21	20		T22	125
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	275394	1			T20	15		T21	65		T22	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	422502	1			T20	19		T22	65		T23	27
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	1897096	1			T20	56		T21	12		T22	171
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	1763373	1			T20	64		T21	54		T22	17
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	425457	1			T21	4		T22	61		T23	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	390046	1			T20	27		T21	11		T22	132
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	274388	1			T20	6		T21	86		T22	14
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	424448	1			T20	17		T22	50		T23	14
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	1882837	1			T20	54		T21	10		T22	194
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	1775598	1			T20	69		T21	51		T22	19
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	425377	1			T22	69		T23	26		T24	71
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	394068	1			T20	21		T21	20		T22	102
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	274366	1			T20	17		T21	86		T22	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	422562	1			T20	9		T22	47		T23	30
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	1886234	1			T20	36		T21	22		T22	134
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	1771945	1			T20	77		T21	85		T22	16
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	429978	1			T21	8		T22	54		T23	23
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	391055	1			T20	6		T21	7		T22	147
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	272040	1			T20	25		T21	45		T22	24
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	423556	1			T20	26		T22	70		T23	26
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	1894035	1			T20	62		T21	6		T22	146
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	1764973	1			T20	63		T21	63		T22	22
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	428581	1			T21	12		T22	71		T23	14
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	390920	1			T20	14		T21	25		T22	135
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	275352	1			T20	13		T21	59		T22	17
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	420947	1			T20	18		T21	2		T22	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	1897628	1			T20	51		T21	31		T22	163
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	1760577	1			T20	69		T21	79		T22	15
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	424377	1			T21	12		T22	63		T23	33
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	393811	1			T20	17		T21	11		T22	137
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	277607	1			T20	15		T21	27		T22	9
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	420808	1			T20	18		T21	7		T22	58
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	1896661	1			T20	55		T21	33		T22	82
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	1762255	1			T20	91		T21	107		T22	15
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	425549	1			T20	5		T21	11		T22	36
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	392890	1			T20	3		T21	1		T22	211
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	277215	1			T20	8		T21	15		T22	23
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	420238	1			T20	8		T22	78		T23	16
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	1889130	1			T20	87		T21	21		T22	149
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	1768980	1			T20	56		T21	57		T22	23
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	423310	1			T20	3		T22	92		T23	28
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	395112	1			T20	14		T21	13		T22	114
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	277443	1			T20	8		T21	74		T22	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	420833	1			T20	2		T21	2		T22	52
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	1887843	1			T20	76		T21	30		T22	180
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	1774551	1			T20	45		T21	85		T22	17
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	426228	1			T20	6		T21	8		T22	46
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	390093	1			T20	21		T21	12		T22	126
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	273550	1			T20	12		T21	27		T22	21
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	422543	1			T20	10		T21	5		T22	55
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	1886183	1			T20	65		T21	23		T22	144
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	1767282	1			T20	38		T21	91		T22	19
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	425534	1			T20	7		T21	6		T22	83
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	394393	1			T20	35		T21	11		T22	129
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	279233	1			T20	21		T21	36		T22	22
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	422183	1			T20	4		T22	48		T23	20
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	1890650	1			T20	54		T21	9		T22	154
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	1768866	1			T20	77		T21	61		T22	22
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	427021	1			T20	1		T22	62		T23	32
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	392571	1			T20	17		T21	16		T22	146
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	277558	1			T20	16		T21	71		T22	17
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	418142	1			T20	5		T21	10		T22	44
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	1899665	1			T20	49		T21	15		T22	111
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	1761687	1			T20	97		T21	87		T22	10
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	426204	1			T21	4		T22	51		T23	31
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	393601	1			T20	17		T21	17		T22	157
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	273478	1			T20	6		T21	35		T22	34
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	420173	1			T20	1		T21	9		T22	82
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	1900654	1			T20	69		T21	30		T22	172
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	1758958	1			T20	76		T21	79		T22	26
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	423591	1			T20	2		T21	10		T22	55
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	392368	1			T20	1		T21	8		T22	121
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	276690	1			T20	7		T21	40		T22	17
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	422547	1			T20	15		T22	54		T23	16
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	1892240	1			T20	95		T21	27		T22	152
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	1767595	1			T20	51		T21	89		T22	17
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	423955	1			T20	12		T21	14		T22	52
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	393142	1			T20	6		T21	7		T22	149
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	275546	1			T20	5		T21	30		T22	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	422330	1			T20	1		T22	62		T23	27
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	1887940	1			T20	33		T21	16		T22	150
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	1777110	1			T20	94		T21	84		T22	25
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	425021	1			T21	10		T22	71		T23	38
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	392076	1			T20	9		T21	6		T22	117
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	274533	1			T20	19		T21	43		T22	12
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	418128	1			T20	15		T21	8		T22	70
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	1892637	1			T20	42		T21	6		T22	153
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	1767900	1			T20	91		T21	68		T22	16
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	426566	1			T22	48		T23	30		T24	61
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	392989	1			T20	17		T21	20		T22	134
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	275140	1			T20	14		T21	71		T22	29
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	419576	1			T20	6		T21	2		T22	65
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	1891401	1			T20	68		T21	19		T22	189
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	1767862	1			T20	79		T21	83		T22	33
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	423923	1			T20	5		T21	2		T22	93
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	393195	1			T20	16		T21	13		T22	62
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	278230	1			T20	2		T21	46		T22	9
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	420197	1			T21	4		T22	59		T23	31
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	1891139	1			T20	43		T21	9		T22	124
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	1771905	1			T20	106		T21	39		T22	30
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	424433	1			T22	55		T23	27		T24	70
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	390762	1			T20	16		T21	24		T22	170
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	275887	1			T20	5		T21	89		T22	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	420682	1			T21	6		T22	59		T23	14
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	1893324	1			T20	49		T21	27		T22	194
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	1768677	1			T20	87		T21	102		T22	14
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	423652	1			T20	8		T22	88		T23	19
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	393030	1			T20	3		T21	8		T22	87
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	273773	1			T20	9		T21	30		T22	19
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	422352	1			T20	14		T22	43		T23	22
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	1888251	1			T20	53		T21	17		T22	161
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	1771605	1			T20	64		T21	58		T22	16
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	426175	1			T20	2		T21	4		T22	38
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	394532	1			T20	24		T21	20		T22	126
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	275209	1			T20	17		T21	62		T22	25
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	419036	1			T20	10		T21	6		T22	79
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	1897324	1			T20	34		T21	26		T22	167
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	1763465	1			T20	95		T21	90		T22	20
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	424123	1			T21	2		T22	64		T23	25
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	392707	1			T20	14		T21	9		T22	113
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	275425	1			T20	19		T21	38		T22	13
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	421764	1			T20	8		T21	2		T22	68

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal