Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[1]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[2]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[3]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[4]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[5]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[6]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[7]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[8]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[9]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[10]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[11]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[12]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[13]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[14]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[15]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[16]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[17]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[18]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[19]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[20]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[21]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[22]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[23]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[24]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[25]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[26]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[27]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[28]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[29]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[30]	5174808	1			T20	170		T21	167		T22	445
bins_for_gpio_bits[31]	5174808	1			T20	170		T21	167		T22	445

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86683266

1

T20

2396

T21

1180

T22

11287

auto[1]

78910590

1

T20

3044

T21

4164

T22

2953

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86676612

1

T20

2397

T21

1180

T22

11287

auto[1]

78917244

1

T20

3043

T21

4164

T22

2953

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	2634757	1			T20	40		T21	31		T22	369
bins_for_gpio_bits[0]	auto[0]	auto[1]	77065	1			T21	1		T22	6		T23	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	77285	1			T21	1		T22	6		T23	6
bins_for_gpio_bits[0]	auto[1]	auto[1]	2385701	1			T20	130		T21	134		T22	64
bins_for_gpio_bits[1]	auto[0]	auto[0]	2621572	1			T20	74		T21	30		T22	336
bins_for_gpio_bits[1]	auto[0]	auto[1]	77051	1			T21	1		T22	11		T23	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	77284	1			T21	1		T22	11		T23	5
bins_for_gpio_bits[1]	auto[1]	auto[1]	2398901	1			T20	96		T21	135		T22	87
bins_for_gpio_bits[2]	auto[0]	auto[0]	2630023	1			T20	104		T21	40		T22	366
bins_for_gpio_bits[2]	auto[0]	auto[1]	77204	1			T21	1		T22	7		T23	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	77371	1			T21	1		T22	7		T23	5
bins_for_gpio_bits[2]	auto[1]	auto[1]	2390210	1			T20	66		T21	125		T22	65
bins_for_gpio_bits[3]	auto[0]	auto[0]	2629607	1			T20	64		T21	30		T22	336
bins_for_gpio_bits[3]	auto[0]	auto[1]	77379	1			T21	1		T22	12		T23	6
bins_for_gpio_bits[3]	auto[1]	auto[0]	77577	1			T21	1		T22	12		T23	7
bins_for_gpio_bits[3]	auto[1]	auto[1]	2390245	1			T20	106		T21	135		T22	85
bins_for_gpio_bits[4]	auto[0]	auto[0]	2634912	1			T20	85		T21	44		T22	346
bins_for_gpio_bits[4]	auto[0]	auto[1]	77117	1			T21	2		T22	10		T23	6
bins_for_gpio_bits[4]	auto[1]	auto[0]	77314	1			T21	2		T22	10		T23	6
bins_for_gpio_bits[4]	auto[1]	auto[1]	2385465	1			T20	85		T21	119		T22	79
bins_for_gpio_bits[5]	auto[0]	auto[0]	2621564	1			T20	84		T21	36		T22	338
bins_for_gpio_bits[5]	auto[0]	auto[1]	77188	1			T21	2		T22	12		T23	7
bins_for_gpio_bits[5]	auto[1]	auto[0]	77402	1			T21	2		T22	12		T23	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	2398654	1			T20	86		T21	127		T22	83
bins_for_gpio_bits[6]	auto[0]	auto[0]	2631293	1			T20	67		T21	33		T22	355
bins_for_gpio_bits[6]	auto[0]	auto[1]	77112	1			T21	2		T22	8		T23	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	77329	1			T21	2		T22	8		T23	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	2389074	1			T20	103		T21	130		T22	74
bins_for_gpio_bits[7]	auto[0]	auto[0]	2629519	1			T20	75		T21	35		T22	366
bins_for_gpio_bits[7]	auto[0]	auto[1]	77150	1			T20	1		T21	2		T22	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	77341	1			T21	2		T22	6		T23	7
bins_for_gpio_bits[7]	auto[1]	auto[1]	2390798	1			T20	94		T21	128		T22	67
bins_for_gpio_bits[8]	auto[0]	auto[0]	2631447	1			T20	74		T21	32		T22	351
bins_for_gpio_bits[8]	auto[0]	auto[1]	76867	1			T21	2		T22	11		T23	5
bins_for_gpio_bits[8]	auto[1]	auto[0]	77071	1			T21	2		T22	11		T23	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	2389423	1			T20	96		T21	131		T22	72
bins_for_gpio_bits[9]	auto[0]	auto[0]	2625525	1			T20	95		T21	28		T22	373
bins_for_gpio_bits[9]	auto[0]	auto[1]	77331	1			T21	1		T22	7		T23	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	77553	1			T21	1		T22	7		T23	5
bins_for_gpio_bits[9]	auto[1]	auto[1]	2394399	1			T20	75		T21	137		T22	58
bins_for_gpio_bits[10]	auto[0]	auto[0]	2635618	1			T20	90		T21	32		T22	348
bins_for_gpio_bits[10]	auto[0]	auto[1]	76786	1			T21	1		T22	10		T23	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	76989	1			T21	1		T22	10		T23	5
bins_for_gpio_bits[10]	auto[1]	auto[1]	2385415	1			T20	80		T21	133		T22	77
bins_for_gpio_bits[11]	auto[0]	auto[0]	2624560	1			T20	64		T21	37		T22	335
bins_for_gpio_bits[11]	auto[0]	auto[1]	76880	1			T21	1		T22	11		T23	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	77065	1			T21	1		T22	11		T23	7
bins_for_gpio_bits[11]	auto[1]	auto[1]	2396303	1			T20	106		T21	128		T22	88
bins_for_gpio_bits[12]	auto[0]	auto[0]	2635515	1			T20	83		T21	26		T22	355
bins_for_gpio_bits[12]	auto[0]	auto[1]	76894	1			T21	1		T22	9		T23	4
bins_for_gpio_bits[12]	auto[1]	auto[0]	77084	1			T21	1		T22	9		T23	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	2385315	1			T20	87		T21	139		T22	72
bins_for_gpio_bits[13]	auto[0]	auto[0]	2624604	1			T20	75		T21	30		T22	354
bins_for_gpio_bits[13]	auto[0]	auto[1]	77447	1			T22	11		T23	5		T24	16
bins_for_gpio_bits[13]	auto[1]	auto[0]	77678	1			T22	11		T23	5		T24	16
bins_for_gpio_bits[13]	auto[1]	auto[1]	2395079	1			T20	95		T21	137		T22	69
bins_for_gpio_bits[14]	auto[0]	auto[0]	2629847	1			T20	42		T21	35		T22	321
bins_for_gpio_bits[14]	auto[0]	auto[1]	77202	1			T21	2		T22	14		T23	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	77420	1			T21	2		T22	14		T23	6
bins_for_gpio_bits[14]	auto[1]	auto[1]	2390339	1			T20	128		T21	128		T22	96
bins_for_gpio_bits[15]	auto[0]	auto[0]	2636413	1			T20	76		T21	40		T22	342
bins_for_gpio_bits[15]	auto[0]	auto[1]	76956	1			T21	3		T22	10		T23	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	77123	1			T21	3		T22	10		T23	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	2384316	1			T20	94		T21	121		T22	83
bins_for_gpio_bits[16]	auto[0]	auto[0]	2638431	1			T20	68		T21	50		T22	351
bins_for_gpio_bits[16]	auto[0]	auto[1]	77172	1			T21	4		T22	12		T23	5
bins_for_gpio_bits[16]	auto[1]	auto[0]	77385	1			T21	4		T22	12		T23	5
bins_for_gpio_bits[16]	auto[1]	auto[1]	2381820	1			T20	102		T21	109		T22	70
bins_for_gpio_bits[17]	auto[0]	auto[0]	2637685	1			T20	63		T21	41		T22	318
bins_for_gpio_bits[17]	auto[0]	auto[1]	77200	1			T21	4		T22	11		T23	5
bins_for_gpio_bits[17]	auto[1]	auto[0]	77415	1			T21	4		T22	11		T23	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	2382508	1			T20	107		T21	118		T22	105
bins_for_gpio_bits[18]	auto[0]	auto[0]	2630451	1			T20	104		T21	34		T22	347
bins_for_gpio_bits[18]	auto[0]	auto[1]	76880	1			T22	8		T23	4		T24	15
bins_for_gpio_bits[18]	auto[1]	auto[0]	77101	1			T22	8		T23	4		T24	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	2390376	1			T20	66		T21	133		T22	82
bins_for_gpio_bits[19]	auto[0]	auto[0]	2626494	1			T20	103		T21	48		T22	340
bins_for_gpio_bits[19]	auto[0]	auto[1]	77483	1			T21	2		T22	12		T23	7
bins_for_gpio_bits[19]	auto[1]	auto[0]	77670	1			T21	2		T22	12		T23	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	2393161	1			T20	67		T21	115		T22	81
bins_for_gpio_bits[20]	auto[0]	auto[0]	2629021	1			T20	107		T21	39		T22	349
bins_for_gpio_bits[20]	auto[0]	auto[1]	76858	1			T21	1		T22	7		T23	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	77089	1			T21	1		T22	7		T23	6
bins_for_gpio_bits[20]	auto[1]	auto[1]	2391840	1			T20	63		T21	126		T22	82
bins_for_gpio_bits[21]	auto[0]	auto[0]	2633109	1			T20	72		T21	25		T22	350
bins_for_gpio_bits[21]	auto[0]	auto[1]	76924	1			T22	12		T23	6		T24	8
bins_for_gpio_bits[21]	auto[1]	auto[0]	77133	1			T22	12		T23	6		T24	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	2387642	1			T20	98		T21	142		T22	71
bins_for_gpio_bits[22]	auto[0]	auto[0]	2641626	1			T20	66		T21	34		T22	305
bins_for_gpio_bits[22]	auto[0]	auto[1]	77611	1			T21	2		T22	14		T23	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	77844	1			T21	2		T22	14		T23	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	2377727	1			T20	104		T21	129		T22	112
bins_for_gpio_bits[23]	auto[0]	auto[0]	2639512	1			T20	72		T21	46		T22	333
bins_for_gpio_bits[23]	auto[0]	auto[1]	76895	1			T21	2		T22	15		T23	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	77101	1			T21	2		T22	15		T23	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	2381300	1			T20	98		T21	117		T22	82
bins_for_gpio_bits[24]	auto[0]	auto[0]	2631913	1			T20	113		T21	45		T22	344
bins_for_gpio_bits[24]	auto[0]	auto[1]	77223	1			T21	3		T22	9		T23	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	77424	1			T21	3		T22	9		T23	6
bins_for_gpio_bits[24]	auto[1]	auto[1]	2388248	1			T20	57		T21	116		T22	83
bins_for_gpio_bits[25]	auto[0]	auto[0]	2627789	1			T20	42		T21	28		T22	324
bins_for_gpio_bits[25]	auto[0]	auto[1]	77004	1			T21	4		T22	14		T23	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	77248	1			T21	4		T22	14		T23	5
bins_for_gpio_bits[25]	auto[1]	auto[1]	2392767	1			T20	128		T21	131		T22	93
bins_for_gpio_bits[26]	auto[0]	auto[0]	2634709	1			T20	59		T21	26		T22	323
bins_for_gpio_bits[26]	auto[0]	auto[1]	77259	1			T22	12		T23	5		T24	14
bins_for_gpio_bits[26]	auto[1]	auto[0]	77483	1			T22	12		T23	6		T24	14
bins_for_gpio_bits[26]	auto[1]	auto[1]	2385357	1			T20	111		T21	141		T22	98
bins_for_gpio_bits[27]	auto[0]	auto[0]	2631502	1			T20	89		T21	33		T22	334
bins_for_gpio_bits[27]	auto[0]	auto[1]	76803	1			T21	1		T22	10		T23	5
bins_for_gpio_bits[27]	auto[1]	auto[0]	77017	1			T21	1		T22	10		T23	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	2389486	1			T20	81		T21	132		T22	91
bins_for_gpio_bits[28]	auto[0]	auto[0]	2629157	1			T20	59		T21	33		T22	341
bins_for_gpio_bits[28]	auto[0]	auto[1]	76983	1			T22	8		T23	3		T24	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	77177	1			T22	8		T23	3		T24	13
bins_for_gpio_bits[28]	auto[1]	auto[1]	2391491	1			T20	111		T21	134		T22	88
bins_for_gpio_bits[29]	auto[0]	auto[0]	2632567	1			T20	59		T21	35		T22	360
bins_for_gpio_bits[29]	auto[0]	auto[1]	77261	1			T20	1		T22	9		T23	7
bins_for_gpio_bits[29]	auto[1]	auto[0]	77439	1			T20	1		T22	9		T23	7
bins_for_gpio_bits[29]	auto[1]	auto[1]	2387541	1			T20	109		T21	132		T22	67
bins_for_gpio_bits[30]	auto[0]	auto[0]	2631748	1			T20	79		T21	39		T22	314
bins_for_gpio_bits[30]	auto[0]	auto[1]	76980	1			T21	2		T22	11		T23	6
bins_for_gpio_bits[30]	auto[1]	auto[0]	77210	1			T21	2		T22	11		T23	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	2388870	1			T20	91		T21	124		T22	109
bins_for_gpio_bits[31]	auto[0]	auto[0]	2636926	1			T20	48		T21	36		T22	331
bins_for_gpio_bits[31]	auto[0]	auto[1]	77031	1			T21	1		T22	13		T23	6
bins_for_gpio_bits[31]	auto[1]	auto[0]	77228	1			T21	1		T22	13		T23	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	2383623	1			T20	122		T21	129		T22	88