Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3533417 |
1 |
|
|
T20 |
96 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1679800 |
1 |
|
|
T20 |
30 |
|
T26 |
178 |
|
T27 |
743 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4996280 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216937 |
1 |
|
|
T26 |
8 |
|
T27 |
191 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3517658 |
1 |
|
|
T20 |
107 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1695559 |
1 |
|
|
T20 |
19 |
|
T26 |
140 |
|
T27 |
1007 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
749495 |
1 |
|
|
T20 |
12 |
|
T26 |
67 |
|
T27 |
419 |
| auto[1] |
auto[0] |
auto[1] |
110243 |
1 |
|
|
T26 |
7 |
|
T27 |
102 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
729127 |
1 |
|
|
T20 |
7 |
|
T26 |
65 |
|
T27 |
397 |
| auto[1] |
auto[1] |
auto[1] |
106694 |
1 |
|
|
T26 |
1 |
|
T27 |
89 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3540943 |
1 |
|
|
T20 |
73 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1672274 |
1 |
|
|
T20 |
53 |
|
T26 |
173 |
|
T27 |
963 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4995928 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217289 |
1 |
|
|
T20 |
1 |
|
T26 |
8 |
|
T27 |
174 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3512998 |
1 |
|
|
T20 |
86 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1700219 |
1 |
|
|
T20 |
40 |
|
T26 |
147 |
|
T27 |
916 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
750298 |
1 |
|
|
T20 |
30 |
|
T26 |
66 |
|
T27 |
241 |
| auto[1] |
auto[0] |
auto[1] |
110014 |
1 |
|
|
T20 |
1 |
|
T26 |
5 |
|
T27 |
57 |
| auto[1] |
auto[1] |
auto[0] |
732632 |
1 |
|
|
T20 |
9 |
|
T26 |
73 |
|
T27 |
501 |
| auto[1] |
auto[1] |
auto[1] |
107275 |
1 |
|
|
T26 |
3 |
|
T27 |
117 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3532848 |
1 |
|
|
T20 |
94 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1680369 |
1 |
|
|
T20 |
32 |
|
T26 |
154 |
|
T27 |
852 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4998123 |
1 |
|
|
T20 |
124 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215094 |
1 |
|
|
T20 |
2 |
|
T26 |
12 |
|
T27 |
148 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3528827 |
1 |
|
|
T20 |
93 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1684390 |
1 |
|
|
T20 |
33 |
|
T26 |
202 |
|
T27 |
762 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
737676 |
1 |
|
|
T20 |
26 |
|
T26 |
111 |
|
T27 |
348 |
| auto[1] |
auto[0] |
auto[1] |
107678 |
1 |
|
|
T20 |
2 |
|
T26 |
9 |
|
T27 |
85 |
| auto[1] |
auto[1] |
auto[0] |
731620 |
1 |
|
|
T20 |
5 |
|
T26 |
79 |
|
T27 |
266 |
| auto[1] |
auto[1] |
auto[1] |
107416 |
1 |
|
|
T26 |
3 |
|
T27 |
63 |
|
T2 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3515832 |
1 |
|
|
T20 |
84 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1697385 |
1 |
|
|
T20 |
42 |
|
T26 |
138 |
|
T27 |
861 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4998530 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
214687 |
1 |
|
|
T20 |
1 |
|
T26 |
12 |
|
T27 |
145 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3529918 |
1 |
|
|
T20 |
92 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1683299 |
1 |
|
|
T20 |
34 |
|
T26 |
196 |
|
T27 |
784 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
731333 |
1 |
|
|
T20 |
24 |
|
T26 |
108 |
|
T27 |
365 |
| auto[1] |
auto[0] |
auto[1] |
107095 |
1 |
|
|
T26 |
9 |
|
T27 |
83 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
737279 |
1 |
|
|
T20 |
9 |
|
T26 |
76 |
|
T27 |
274 |
| auto[1] |
auto[1] |
auto[1] |
107592 |
1 |
|
|
T20 |
1 |
|
T26 |
3 |
|
T27 |
62 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511855 |
1 |
|
|
T20 |
84 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701362 |
1 |
|
|
T20 |
42 |
|
T26 |
191 |
|
T27 |
938 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4996832 |
1 |
|
|
T20 |
124 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216385 |
1 |
|
|
T20 |
2 |
|
T26 |
11 |
|
T27 |
192 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3517079 |
1 |
|
|
T20 |
77 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1696138 |
1 |
|
|
T20 |
49 |
|
T26 |
185 |
|
T27 |
959 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
738740 |
1 |
|
|
T20 |
27 |
|
T26 |
76 |
|
T27 |
352 |
| auto[1] |
auto[0] |
auto[1] |
107966 |
1 |
|
|
T20 |
1 |
|
T26 |
5 |
|
T27 |
87 |
| auto[1] |
auto[1] |
auto[0] |
741013 |
1 |
|
|
T20 |
20 |
|
T26 |
98 |
|
T27 |
415 |
| auto[1] |
auto[1] |
auto[1] |
108419 |
1 |
|
|
T20 |
1 |
|
T26 |
6 |
|
T27 |
105 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511173 |
1 |
|
|
T20 |
102 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1702044 |
1 |
|
|
T20 |
24 |
|
T26 |
235 |
|
T27 |
900 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997844 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215373 |
1 |
|
|
T26 |
10 |
|
T27 |
183 |
|
T2 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523050 |
1 |
|
|
T20 |
117 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690167 |
1 |
|
|
T20 |
9 |
|
T26 |
144 |
|
T27 |
932 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
733523 |
1 |
|
|
T26 |
55 |
|
T27 |
375 |
|
T1 |
24 |
| auto[1] |
auto[0] |
auto[1] |
106578 |
1 |
|
|
T26 |
4 |
|
T27 |
89 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
741271 |
1 |
|
|
T20 |
9 |
|
T26 |
79 |
|
T27 |
374 |
| auto[1] |
auto[1] |
auto[1] |
108795 |
1 |
|
|
T26 |
6 |
|
T27 |
94 |
|
T2 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523037 |
1 |
|
|
T20 |
85 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690180 |
1 |
|
|
T20 |
41 |
|
T26 |
216 |
|
T27 |
988 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4995513 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217704 |
1 |
|
|
T26 |
9 |
|
T27 |
180 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3512795 |
1 |
|
|
T20 |
103 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1700422 |
1 |
|
|
T20 |
23 |
|
T26 |
174 |
|
T27 |
937 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
748606 |
1 |
|
|
T20 |
5 |
|
T26 |
65 |
|
T27 |
298 |
| auto[1] |
auto[0] |
auto[1] |
110393 |
1 |
|
|
T26 |
4 |
|
T27 |
75 |
|
T2 |
3 |
| auto[1] |
auto[1] |
auto[0] |
734112 |
1 |
|
|
T20 |
18 |
|
T26 |
100 |
|
T27 |
459 |
| auto[1] |
auto[1] |
auto[1] |
107311 |
1 |
|
|
T26 |
5 |
|
T27 |
105 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3516230 |
1 |
|
|
T20 |
101 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1696987 |
1 |
|
|
T20 |
25 |
|
T26 |
192 |
|
T27 |
987 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997248 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215969 |
1 |
|
|
T26 |
13 |
|
T27 |
148 |
|
T2 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3518752 |
1 |
|
|
T20 |
95 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1694465 |
1 |
|
|
T20 |
31 |
|
T26 |
166 |
|
T27 |
735 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
736024 |
1 |
|
|
T20 |
21 |
|
T26 |
57 |
|
T27 |
216 |
| auto[1] |
auto[0] |
auto[1] |
106935 |
1 |
|
|
T26 |
6 |
|
T27 |
52 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
742472 |
1 |
|
|
T20 |
10 |
|
T26 |
96 |
|
T27 |
371 |
| auto[1] |
auto[1] |
auto[1] |
109034 |
1 |
|
|
T26 |
7 |
|
T27 |
96 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3524937 |
1 |
|
|
T20 |
65 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1688280 |
1 |
|
|
T20 |
61 |
|
T26 |
224 |
|
T27 |
705 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997051 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216166 |
1 |
|
|
T26 |
11 |
|
T27 |
185 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3522985 |
1 |
|
|
T20 |
88 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690232 |
1 |
|
|
T20 |
38 |
|
T26 |
177 |
|
T27 |
869 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
737897 |
1 |
|
|
T20 |
21 |
|
T26 |
63 |
|
T27 |
375 |
| auto[1] |
auto[0] |
auto[1] |
107696 |
1 |
|
|
T26 |
1 |
|
T27 |
88 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
736169 |
1 |
|
|
T20 |
17 |
|
T26 |
103 |
|
T27 |
309 |
| auto[1] |
auto[1] |
auto[1] |
108470 |
1 |
|
|
T26 |
10 |
|
T27 |
97 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3516784 |
1 |
|
|
T20 |
72 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1696433 |
1 |
|
|
T20 |
54 |
|
T26 |
195 |
|
T27 |
592 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4995565 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217652 |
1 |
|
|
T20 |
1 |
|
T26 |
9 |
|
T27 |
152 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511629 |
1 |
|
|
T20 |
79 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701588 |
1 |
|
|
T20 |
47 |
|
T26 |
157 |
|
T27 |
798 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
738630 |
1 |
|
|
T20 |
19 |
|
T26 |
48 |
|
T27 |
432 |
| auto[1] |
auto[0] |
auto[1] |
108460 |
1 |
|
|
T20 |
1 |
|
T26 |
3 |
|
T27 |
96 |
| auto[1] |
auto[1] |
auto[0] |
745306 |
1 |
|
|
T20 |
27 |
|
T26 |
100 |
|
T27 |
214 |
| auto[1] |
auto[1] |
auto[1] |
109192 |
1 |
|
|
T26 |
6 |
|
T27 |
56 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3540367 |
1 |
|
|
T20 |
81 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1672850 |
1 |
|
|
T20 |
45 |
|
T26 |
119 |
|
T27 |
982 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4995554 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217663 |
1 |
|
|
T26 |
14 |
|
T27 |
159 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3512075 |
1 |
|
|
T20 |
92 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701142 |
1 |
|
|
T20 |
34 |
|
T26 |
219 |
|
T27 |
815 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
751339 |
1 |
|
|
T20 |
20 |
|
T26 |
131 |
|
T27 |
270 |
| auto[1] |
auto[0] |
auto[1] |
110252 |
1 |
|
|
T26 |
12 |
|
T27 |
63 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
732140 |
1 |
|
|
T20 |
14 |
|
T26 |
74 |
|
T27 |
386 |
| auto[1] |
auto[1] |
auto[1] |
107411 |
1 |
|
|
T26 |
2 |
|
T27 |
96 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3527120 |
1 |
|
|
T20 |
79 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1686097 |
1 |
|
|
T20 |
47 |
|
T26 |
105 |
|
T27 |
955 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4995676 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217541 |
1 |
|
|
T20 |
1 |
|
T26 |
15 |
|
T27 |
131 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3512946 |
1 |
|
|
T20 |
89 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1700271 |
1 |
|
|
T20 |
37 |
|
T26 |
194 |
|
T27 |
633 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
744911 |
1 |
|
|
T20 |
22 |
|
T26 |
123 |
|
T27 |
193 |
| auto[1] |
auto[0] |
auto[1] |
109157 |
1 |
|
|
T20 |
1 |
|
T26 |
11 |
|
T27 |
46 |
| auto[1] |
auto[1] |
auto[0] |
737819 |
1 |
|
|
T20 |
14 |
|
T26 |
56 |
|
T27 |
309 |
| auto[1] |
auto[1] |
auto[1] |
108384 |
1 |
|
|
T26 |
4 |
|
T27 |
85 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3519885 |
1 |
|
|
T20 |
91 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1693332 |
1 |
|
|
T20 |
35 |
|
T26 |
117 |
|
T27 |
527 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4999152 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
214065 |
1 |
|
|
T26 |
7 |
|
T27 |
164 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3532674 |
1 |
|
|
T20 |
79 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1680543 |
1 |
|
|
T20 |
47 |
|
T26 |
120 |
|
T27 |
877 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
730243 |
1 |
|
|
T20 |
34 |
|
T26 |
68 |
|
T27 |
537 |
| auto[1] |
auto[0] |
auto[1] |
105597 |
1 |
|
|
T26 |
4 |
|
T27 |
123 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
736235 |
1 |
|
|
T20 |
13 |
|
T26 |
45 |
|
T27 |
176 |
| auto[1] |
auto[1] |
auto[1] |
108468 |
1 |
|
|
T26 |
3 |
|
T27 |
41 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523464 |
1 |
|
|
T20 |
83 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1689753 |
1 |
|
|
T20 |
43 |
|
T26 |
203 |
|
T27 |
969 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5001494 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
211723 |
1 |
|
|
T26 |
9 |
|
T27 |
206 |
|
T2 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3550889 |
1 |
|
|
T20 |
105 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1662328 |
1 |
|
|
T20 |
21 |
|
T26 |
158 |
|
T27 |
1088 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
729903 |
1 |
|
|
T20 |
13 |
|
T26 |
60 |
|
T27 |
369 |
| auto[1] |
auto[0] |
auto[1] |
106505 |
1 |
|
|
T26 |
3 |
|
T27 |
83 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
720702 |
1 |
|
|
T20 |
8 |
|
T26 |
89 |
|
T27 |
513 |
| auto[1] |
auto[1] |
auto[1] |
105218 |
1 |
|
|
T26 |
6 |
|
T27 |
123 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3525913 |
1 |
|
|
T20 |
105 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1687304 |
1 |
|
|
T20 |
21 |
|
T26 |
163 |
|
T27 |
885 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4996656 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216561 |
1 |
|
|
T26 |
8 |
|
T27 |
174 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3516105 |
1 |
|
|
T20 |
99 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1697112 |
1 |
|
|
T20 |
27 |
|
T26 |
194 |
|
T27 |
868 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
740962 |
1 |
|
|
T20 |
27 |
|
T26 |
86 |
|
T27 |
413 |
| auto[1] |
auto[0] |
auto[1] |
108447 |
1 |
|
|
T26 |
5 |
|
T27 |
102 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
739589 |
1 |
|
|
T26 |
100 |
|
T27 |
281 |
|
T1 |
12 |
| auto[1] |
auto[1] |
auto[1] |
108114 |
1 |
|
|
T26 |
3 |
|
T27 |
72 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3525862 |
1 |
|
|
T20 |
85 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1687355 |
1 |
|
|
T20 |
41 |
|
T26 |
201 |
|
T27 |
818 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4996515 |
1 |
|
|
T20 |
124 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216702 |
1 |
|
|
T20 |
2 |
|
T26 |
10 |
|
T27 |
167 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3513363 |
1 |
|
|
T20 |
77 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1699854 |
1 |
|
|
T20 |
49 |
|
T26 |
157 |
|
T27 |
822 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
743575 |
1 |
|
|
T20 |
29 |
|
T26 |
64 |
|
T27 |
341 |
| auto[1] |
auto[0] |
auto[1] |
108443 |
1 |
|
|
T20 |
2 |
|
T26 |
5 |
|
T27 |
85 |
| auto[1] |
auto[1] |
auto[0] |
739577 |
1 |
|
|
T20 |
18 |
|
T26 |
83 |
|
T27 |
314 |
| auto[1] |
auto[1] |
auto[1] |
108259 |
1 |
|
|
T26 |
5 |
|
T27 |
82 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3518204 |
1 |
|
|
T20 |
96 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1695013 |
1 |
|
|
T20 |
30 |
|
T26 |
211 |
|
T27 |
1085 |