Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511619 |
1 |
|
|
T20 |
92 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701598 |
1 |
|
|
T20 |
34 |
|
T26 |
223 |
|
T27 |
847 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4996065 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217152 |
1 |
|
|
T20 |
1 |
|
T26 |
10 |
|
T27 |
193 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3512126 |
1 |
|
|
T20 |
91 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701091 |
1 |
|
|
T20 |
35 |
|
T26 |
154 |
|
T27 |
971 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
737287 |
1 |
|
|
T20 |
18 |
|
T26 |
46 |
|
T27 |
421 |
| auto[1] |
auto[0] |
auto[1] |
107406 |
1 |
|
|
T20 |
1 |
|
T26 |
2 |
|
T27 |
104 |
| auto[1] |
auto[1] |
auto[0] |
746652 |
1 |
|
|
T20 |
16 |
|
T26 |
98 |
|
T27 |
357 |
| auto[1] |
auto[1] |
auto[1] |
109746 |
1 |
|
|
T26 |
8 |
|
T27 |
89 |
|
T2 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |