Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3520099 |
1 |
|
|
T20 |
98 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1693118 |
1 |
|
|
T20 |
28 |
|
T26 |
201 |
|
T27 |
1155 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4999129 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
214088 |
1 |
|
|
T26 |
10 |
|
T27 |
116 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3537433 |
1 |
|
|
T20 |
103 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1675784 |
1 |
|
|
T20 |
23 |
|
T26 |
193 |
|
T27 |
660 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
730138 |
1 |
|
|
T20 |
10 |
|
T26 |
73 |
|
T27 |
177 |
| auto[1] |
auto[0] |
auto[1] |
106797 |
1 |
|
|
T26 |
4 |
|
T27 |
34 |
|
T2 |
10 |
| auto[1] |
auto[1] |
auto[0] |
731558 |
1 |
|
|
T20 |
13 |
|
T26 |
110 |
|
T27 |
367 |
| auto[1] |
auto[1] |
auto[1] |
107291 |
1 |
|
|
T26 |
6 |
|
T27 |
82 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |