Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3515659 |
1 |
|
|
T20 |
82 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1697558 |
1 |
|
|
T20 |
44 |
|
T26 |
199 |
|
T27 |
656 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997122 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216095 |
1 |
|
|
T26 |
11 |
|
T27 |
162 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523817 |
1 |
|
|
T20 |
87 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1689400 |
1 |
|
|
T20 |
39 |
|
T26 |
197 |
|
T27 |
867 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
734742 |
1 |
|
|
T20 |
23 |
|
T26 |
82 |
|
T27 |
445 |
| auto[1] |
auto[0] |
auto[1] |
107918 |
1 |
|
|
T26 |
3 |
|
T27 |
102 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
738563 |
1 |
|
|
T20 |
16 |
|
T26 |
104 |
|
T27 |
260 |
| auto[1] |
auto[1] |
auto[1] |
108177 |
1 |
|
|
T26 |
8 |
|
T27 |
60 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |