Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511288 |
1 |
|
|
T20 |
82 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701929 |
1 |
|
|
T20 |
44 |
|
T26 |
120 |
|
T27 |
722 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997305 |
1 |
|
|
T20 |
122 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215912 |
1 |
|
|
T20 |
4 |
|
T26 |
8 |
|
T27 |
127 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3521704 |
1 |
|
|
T20 |
82 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1691513 |
1 |
|
|
T20 |
44 |
|
T26 |
140 |
|
T27 |
705 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
733917 |
1 |
|
|
T20 |
24 |
|
T26 |
85 |
|
T27 |
273 |
| auto[1] |
auto[0] |
auto[1] |
106635 |
1 |
|
|
T20 |
2 |
|
T26 |
5 |
|
T27 |
63 |
| auto[1] |
auto[1] |
auto[0] |
741684 |
1 |
|
|
T20 |
16 |
|
T26 |
47 |
|
T27 |
305 |
| auto[1] |
auto[1] |
auto[1] |
109277 |
1 |
|
|
T20 |
2 |
|
T26 |
3 |
|
T27 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |