Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3507305 |
1 |
|
|
T20 |
87 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1705912 |
1 |
|
|
T20 |
39 |
|
T26 |
190 |
|
T27 |
777 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997096 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216121 |
1 |
|
|
T26 |
17 |
|
T27 |
173 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3521631 |
1 |
|
|
T20 |
105 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1691586 |
1 |
|
|
T20 |
21 |
|
T26 |
244 |
|
T27 |
887 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
735168 |
1 |
|
|
T20 |
10 |
|
T26 |
100 |
|
T27 |
409 |
| auto[1] |
auto[0] |
auto[1] |
107263 |
1 |
|
|
T26 |
9 |
|
T27 |
95 |
|
T2 |
6 |
| auto[1] |
auto[1] |
auto[0] |
740297 |
1 |
|
|
T20 |
11 |
|
T26 |
127 |
|
T27 |
305 |
| auto[1] |
auto[1] |
auto[1] |
108858 |
1 |
|
|
T26 |
8 |
|
T27 |
78 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |