Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511224 |
1 |
|
|
T20 |
70 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701993 |
1 |
|
|
T20 |
56 |
|
T26 |
192 |
|
T27 |
823 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4995958 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217259 |
1 |
|
|
T20 |
1 |
|
T26 |
18 |
|
T27 |
205 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3514412 |
1 |
|
|
T20 |
97 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1698805 |
1 |
|
|
T20 |
29 |
|
T26 |
150 |
|
T27 |
1115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
740727 |
1 |
|
|
T20 |
12 |
|
T26 |
53 |
|
T27 |
543 |
| auto[1] |
auto[0] |
auto[1] |
108426 |
1 |
|
|
T26 |
8 |
|
T27 |
113 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
740819 |
1 |
|
|
T20 |
16 |
|
T26 |
79 |
|
T27 |
367 |
| auto[1] |
auto[1] |
auto[1] |
108833 |
1 |
|
|
T20 |
1 |
|
T26 |
10 |
|
T27 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |