Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3533417 |
1 |
|
|
T20 |
96 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1679800 |
1 |
|
|
T20 |
30 |
|
T26 |
178 |
|
T27 |
743 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4410645 |
1 |
|
|
T20 |
106 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
802572 |
1 |
|
|
T20 |
20 |
|
T26 |
79 |
|
T27 |
427 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3536288 |
1 |
|
|
T20 |
104 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1676929 |
1 |
|
|
T20 |
22 |
|
T26 |
155 |
|
T27 |
837 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
442806 |
1 |
|
|
T20 |
1 |
|
T26 |
30 |
|
T27 |
223 |
| auto[1] |
auto[0] |
auto[1] |
405026 |
1 |
|
|
T20 |
14 |
|
T26 |
47 |
|
T27 |
211 |
| auto[1] |
auto[1] |
auto[0] |
431551 |
1 |
|
|
T20 |
1 |
|
T26 |
46 |
|
T27 |
187 |
| auto[1] |
auto[1] |
auto[1] |
397546 |
1 |
|
|
T20 |
6 |
|
T26 |
32 |
|
T27 |
216 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |