Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3540943 |
1 |
|
|
T20 |
73 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1672274 |
1 |
|
|
T20 |
53 |
|
T26 |
173 |
|
T27 |
963 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4409504 |
1 |
|
|
T20 |
102 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
803713 |
1 |
|
|
T20 |
24 |
|
T26 |
70 |
|
T27 |
368 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3531156 |
1 |
|
|
T20 |
94 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1682061 |
1 |
|
|
T20 |
32 |
|
T26 |
196 |
|
T27 |
709 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
443745 |
1 |
|
|
T20 |
5 |
|
T26 |
71 |
|
T27 |
155 |
| auto[1] |
auto[0] |
auto[1] |
404376 |
1 |
|
|
T20 |
12 |
|
T26 |
33 |
|
T27 |
146 |
| auto[1] |
auto[1] |
auto[0] |
434603 |
1 |
|
|
T20 |
3 |
|
T26 |
55 |
|
T27 |
186 |
| auto[1] |
auto[1] |
auto[1] |
399337 |
1 |
|
|
T20 |
12 |
|
T26 |
37 |
|
T27 |
222 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |