Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997919 |
1 |
|
|
T20 |
124 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215298 |
1 |
|
|
T20 |
2 |
|
T26 |
10 |
|
T27 |
142 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3528527 |
1 |
|
|
T20 |
91 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1684690 |
1 |
|
|
T20 |
35 |
|
T26 |
178 |
|
T27 |
721 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
740981 |
1 |
|
|
T20 |
28 |
|
T26 |
69 |
|
T27 |
162 |
| auto[1] |
auto[0] |
auto[1] |
107936 |
1 |
|
|
T20 |
2 |
|
T26 |
3 |
|
T27 |
45 |
| auto[1] |
auto[1] |
auto[0] |
728411 |
1 |
|
|
T20 |
5 |
|
T26 |
99 |
|
T27 |
417 |
| auto[1] |
auto[1] |
auto[1] |
107362 |
1 |
|
|
T26 |
7 |
|
T27 |
97 |
|
T2 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |