Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3532848 |
1 |
|
|
T20 |
94 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1680369 |
1 |
|
|
T20 |
32 |
|
T26 |
154 |
|
T27 |
852 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4416511 |
1 |
|
|
T20 |
105 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
796706 |
1 |
|
|
T20 |
21 |
|
T26 |
75 |
|
T27 |
480 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3544212 |
1 |
|
|
T20 |
100 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1669005 |
1 |
|
|
T20 |
26 |
|
T26 |
172 |
|
T27 |
887 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
437801 |
1 |
|
|
T20 |
3 |
|
T26 |
56 |
|
T27 |
187 |
| auto[1] |
auto[0] |
auto[1] |
400177 |
1 |
|
|
T20 |
20 |
|
T26 |
30 |
|
T27 |
205 |
| auto[1] |
auto[1] |
auto[0] |
434498 |
1 |
|
|
T20 |
2 |
|
T26 |
41 |
|
T27 |
220 |
| auto[1] |
auto[1] |
auto[1] |
396529 |
1 |
|
|
T20 |
1 |
|
T26 |
45 |
|
T27 |
275 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |