Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3515832 |
1 |
|
|
T20 |
84 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1697385 |
1 |
|
|
T20 |
42 |
|
T26 |
138 |
|
T27 |
861 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4408943 |
1 |
|
|
T20 |
107 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
804274 |
1 |
|
|
T20 |
19 |
|
T26 |
137 |
|
T27 |
564 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3530282 |
1 |
|
|
T20 |
103 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1682935 |
1 |
|
|
T20 |
23 |
|
T26 |
200 |
|
T27 |
1083 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
439855 |
1 |
|
|
T20 |
2 |
|
T26 |
46 |
|
T27 |
256 |
| auto[1] |
auto[0] |
auto[1] |
403671 |
1 |
|
|
T20 |
14 |
|
T26 |
91 |
|
T27 |
224 |
| auto[1] |
auto[1] |
auto[0] |
438806 |
1 |
|
|
T20 |
2 |
|
T26 |
17 |
|
T27 |
263 |
| auto[1] |
auto[1] |
auto[1] |
400603 |
1 |
|
|
T20 |
5 |
|
T26 |
46 |
|
T27 |
340 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |