Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511855 |
1 |
|
|
T20 |
84 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701362 |
1 |
|
|
T20 |
42 |
|
T26 |
191 |
|
T27 |
938 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4398551 |
1 |
|
|
T20 |
109 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
814666 |
1 |
|
|
T20 |
17 |
|
T26 |
113 |
|
T27 |
409 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3512016 |
1 |
|
|
T20 |
104 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1701201 |
1 |
|
|
T20 |
22 |
|
T26 |
211 |
|
T27 |
825 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
435829 |
1 |
|
|
T20 |
4 |
|
T26 |
39 |
|
T27 |
189 |
| auto[1] |
auto[0] |
auto[1] |
402485 |
1 |
|
|
T20 |
9 |
|
T26 |
60 |
|
T27 |
152 |
| auto[1] |
auto[1] |
auto[0] |
450706 |
1 |
|
|
T20 |
1 |
|
T26 |
59 |
|
T27 |
227 |
| auto[1] |
auto[1] |
auto[1] |
412181 |
1 |
|
|
T20 |
8 |
|
T26 |
53 |
|
T27 |
257 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |