Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3511173 |
1 |
|
|
T20 |
102 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1702044 |
1 |
|
|
T20 |
24 |
|
T26 |
235 |
|
T27 |
900 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4397944 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
815273 |
1 |
|
|
T20 |
1 |
|
T26 |
55 |
|
T27 |
462 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3503772 |
1 |
|
|
T20 |
111 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1709445 |
1 |
|
|
T20 |
15 |
|
T26 |
167 |
|
T27 |
987 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
445903 |
1 |
|
|
T20 |
5 |
|
T26 |
34 |
|
T27 |
272 |
| auto[1] |
auto[0] |
auto[1] |
407736 |
1 |
|
|
T26 |
16 |
|
T27 |
226 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
448269 |
1 |
|
|
T20 |
9 |
|
T26 |
78 |
|
T27 |
253 |
| auto[1] |
auto[1] |
auto[1] |
407537 |
1 |
|
|
T20 |
1 |
|
T26 |
39 |
|
T27 |
236 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |