Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523037 |
1 |
|
|
T20 |
85 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690180 |
1 |
|
|
T20 |
41 |
|
T26 |
216 |
|
T27 |
988 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4411775 |
1 |
|
|
T20 |
104 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
801442 |
1 |
|
|
T20 |
22 |
|
T26 |
104 |
|
T27 |
535 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3530015 |
1 |
|
|
T20 |
97 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1683202 |
1 |
|
|
T20 |
29 |
|
T26 |
205 |
|
T27 |
970 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
446458 |
1 |
|
|
T20 |
7 |
|
T26 |
40 |
|
T27 |
204 |
| auto[1] |
auto[0] |
auto[1] |
403174 |
1 |
|
|
T20 |
9 |
|
T26 |
29 |
|
T27 |
215 |
| auto[1] |
auto[1] |
auto[0] |
435302 |
1 |
|
|
T26 |
61 |
|
T27 |
231 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[1] |
398268 |
1 |
|
|
T20 |
13 |
|
T26 |
75 |
|
T27 |
320 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |