Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3524937 |
1 |
|
|
T20 |
65 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1688280 |
1 |
|
|
T20 |
61 |
|
T26 |
224 |
|
T27 |
705 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4407952 |
1 |
|
|
T20 |
110 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
805265 |
1 |
|
|
T20 |
16 |
|
T26 |
81 |
|
T27 |
344 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3528662 |
1 |
|
|
T20 |
105 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1684555 |
1 |
|
|
T20 |
21 |
|
T26 |
181 |
|
T27 |
665 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
441468 |
1 |
|
|
T26 |
30 |
|
T27 |
215 |
|
T1 |
4 |
| auto[1] |
auto[0] |
auto[1] |
401320 |
1 |
|
|
T26 |
20 |
|
T27 |
245 |
|
T1 |
7 |
| auto[1] |
auto[1] |
auto[0] |
437822 |
1 |
|
|
T20 |
5 |
|
T26 |
70 |
|
T27 |
106 |
| auto[1] |
auto[1] |
auto[1] |
403945 |
1 |
|
|
T20 |
16 |
|
T26 |
61 |
|
T27 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |