Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3516784 |
1 |
|
|
T20 |
72 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1696433 |
1 |
|
|
T20 |
54 |
|
T26 |
195 |
|
T27 |
592 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4396017 |
1 |
|
|
T20 |
112 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
817200 |
1 |
|
|
T20 |
14 |
|
T26 |
115 |
|
T27 |
509 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3502721 |
1 |
|
|
T20 |
111 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1710496 |
1 |
|
|
T20 |
15 |
|
T26 |
197 |
|
T27 |
936 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
444152 |
1 |
|
|
T26 |
45 |
|
T27 |
282 |
|
T1 |
7 |
| auto[1] |
auto[0] |
auto[1] |
403629 |
1 |
|
|
T20 |
5 |
|
T26 |
56 |
|
T27 |
325 |
| auto[1] |
auto[1] |
auto[0] |
449144 |
1 |
|
|
T20 |
1 |
|
T26 |
37 |
|
T27 |
145 |
| auto[1] |
auto[1] |
auto[1] |
413571 |
1 |
|
|
T20 |
9 |
|
T26 |
59 |
|
T27 |
184 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |