Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3540367 |
1 |
|
|
T20 |
81 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1672850 |
1 |
|
|
T20 |
45 |
|
T26 |
119 |
|
T27 |
982 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4410088 |
1 |
|
|
T20 |
118 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
803129 |
1 |
|
|
T20 |
8 |
|
T26 |
115 |
|
T27 |
545 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3531481 |
1 |
|
|
T20 |
94 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1681736 |
1 |
|
|
T20 |
32 |
|
T26 |
174 |
|
T27 |
1071 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
443447 |
1 |
|
|
T20 |
19 |
|
T26 |
33 |
|
T27 |
153 |
| auto[1] |
auto[0] |
auto[1] |
404844 |
1 |
|
|
T20 |
1 |
|
T26 |
80 |
|
T27 |
194 |
| auto[1] |
auto[1] |
auto[0] |
435160 |
1 |
|
|
T20 |
5 |
|
T26 |
26 |
|
T27 |
373 |
| auto[1] |
auto[1] |
auto[1] |
398285 |
1 |
|
|
T20 |
7 |
|
T26 |
35 |
|
T27 |
351 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |