Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3527120 |
1 |
|
|
T20 |
79 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1686097 |
1 |
|
|
T20 |
47 |
|
T26 |
105 |
|
T27 |
955 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4408742 |
1 |
|
|
T20 |
110 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
804475 |
1 |
|
|
T20 |
16 |
|
T26 |
74 |
|
T27 |
466 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3528297 |
1 |
|
|
T20 |
103 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1684920 |
1 |
|
|
T20 |
23 |
|
T26 |
170 |
|
T27 |
979 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
446310 |
1 |
|
|
T26 |
74 |
|
T27 |
201 |
|
T1 |
3 |
| auto[1] |
auto[0] |
auto[1] |
407460 |
1 |
|
|
T20 |
10 |
|
T26 |
39 |
|
T27 |
185 |
| auto[1] |
auto[1] |
auto[0] |
434135 |
1 |
|
|
T20 |
7 |
|
T26 |
22 |
|
T27 |
312 |
| auto[1] |
auto[1] |
auto[1] |
397015 |
1 |
|
|
T20 |
6 |
|
T26 |
35 |
|
T27 |
281 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |