Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3526047 |
1 |
|
|
T20 |
60 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1687170 |
1 |
|
|
T20 |
66 |
|
T26 |
140 |
|
T27 |
991 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5001488 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
211729 |
1 |
|
|
T20 |
1 |
|
T26 |
7 |
|
T27 |
147 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3549601 |
1 |
|
|
T20 |
80 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1663616 |
1 |
|
|
T20 |
46 |
|
T26 |
171 |
|
T27 |
787 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
735258 |
1 |
|
|
T20 |
25 |
|
T26 |
105 |
|
T27 |
250 |
| auto[1] |
auto[0] |
auto[1] |
107137 |
1 |
|
|
T20 |
1 |
|
T26 |
4 |
|
T27 |
59 |
| auto[1] |
auto[1] |
auto[0] |
716629 |
1 |
|
|
T20 |
20 |
|
T26 |
59 |
|
T27 |
390 |
| auto[1] |
auto[1] |
auto[1] |
104592 |
1 |
|
|
T26 |
3 |
|
T27 |
88 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |