Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3519885 |
1 |
|
|
T20 |
91 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1693332 |
1 |
|
|
T20 |
35 |
|
T26 |
117 |
|
T27 |
527 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4407359 |
1 |
|
|
T20 |
116 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
805858 |
1 |
|
|
T20 |
10 |
|
T26 |
104 |
|
T27 |
382 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523112 |
1 |
|
|
T20 |
91 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690105 |
1 |
|
|
T20 |
35 |
|
T26 |
186 |
|
T27 |
787 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
445011 |
1 |
|
|
T20 |
17 |
|
T26 |
43 |
|
T27 |
278 |
| auto[1] |
auto[0] |
auto[1] |
406520 |
1 |
|
|
T20 |
6 |
|
T26 |
70 |
|
T27 |
268 |
| auto[1] |
auto[1] |
auto[0] |
439236 |
1 |
|
|
T20 |
8 |
|
T26 |
39 |
|
T27 |
127 |
| auto[1] |
auto[1] |
auto[1] |
399338 |
1 |
|
|
T20 |
4 |
|
T26 |
34 |
|
T27 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |