Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523464 |
1 |
|
|
T20 |
83 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1689753 |
1 |
|
|
T20 |
43 |
|
T26 |
203 |
|
T27 |
969 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4414955 |
1 |
|
|
T20 |
113 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
798262 |
1 |
|
|
T20 |
13 |
|
T26 |
65 |
|
T27 |
536 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3547218 |
1 |
|
|
T20 |
97 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1665999 |
1 |
|
|
T20 |
29 |
|
T26 |
155 |
|
T27 |
1022 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
436413 |
1 |
|
|
T20 |
15 |
|
T26 |
30 |
|
T27 |
209 |
| auto[1] |
auto[0] |
auto[1] |
401172 |
1 |
|
|
T20 |
5 |
|
T26 |
31 |
|
T27 |
253 |
| auto[1] |
auto[1] |
auto[0] |
431324 |
1 |
|
|
T20 |
1 |
|
T26 |
60 |
|
T27 |
277 |
| auto[1] |
auto[1] |
auto[1] |
397090 |
1 |
|
|
T20 |
8 |
|
T26 |
34 |
|
T27 |
283 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |