Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3525913 |
1 |
|
|
T20 |
105 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1687304 |
1 |
|
|
T20 |
21 |
|
T26 |
163 |
|
T27 |
885 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4407130 |
1 |
|
|
T20 |
118 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
806087 |
1 |
|
|
T20 |
8 |
|
T26 |
105 |
|
T27 |
401 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3522556 |
1 |
|
|
T20 |
108 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690661 |
1 |
|
|
T20 |
18 |
|
T26 |
183 |
|
T27 |
810 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
444815 |
1 |
|
|
T20 |
8 |
|
T26 |
54 |
|
T27 |
215 |
| auto[1] |
auto[0] |
auto[1] |
402893 |
1 |
|
|
T20 |
4 |
|
T26 |
55 |
|
T27 |
234 |
| auto[1] |
auto[1] |
auto[0] |
439759 |
1 |
|
|
T20 |
2 |
|
T26 |
24 |
|
T27 |
194 |
| auto[1] |
auto[1] |
auto[1] |
403194 |
1 |
|
|
T20 |
4 |
|
T26 |
50 |
|
T27 |
167 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |