Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3525862 |
1 |
|
|
T20 |
85 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1687355 |
1 |
|
|
T20 |
41 |
|
T26 |
201 |
|
T27 |
818 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4410662 |
1 |
|
|
T20 |
104 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
802555 |
1 |
|
|
T20 |
22 |
|
T26 |
131 |
|
T27 |
386 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3529973 |
1 |
|
|
T20 |
100 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1683244 |
1 |
|
|
T20 |
26 |
|
T26 |
216 |
|
T27 |
824 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
445501 |
1 |
|
|
T20 |
4 |
|
T26 |
33 |
|
T27 |
256 |
| auto[1] |
auto[0] |
auto[1] |
403898 |
1 |
|
|
T20 |
14 |
|
T26 |
42 |
|
T27 |
219 |
| auto[1] |
auto[1] |
auto[0] |
435188 |
1 |
|
|
T26 |
52 |
|
T27 |
182 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
398657 |
1 |
|
|
T20 |
8 |
|
T26 |
89 |
|
T27 |
167 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |