Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3518204 |
1 |
|
|
T20 |
96 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1695013 |
1 |
|
|
T20 |
30 |
|
T26 |
211 |
|
T27 |
1085 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4401740 |
1 |
|
|
T20 |
114 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
811477 |
1 |
|
|
T20 |
12 |
|
T26 |
98 |
|
T27 |
369 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3516501 |
1 |
|
|
T20 |
109 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1696716 |
1 |
|
|
T20 |
17 |
|
T26 |
167 |
|
T27 |
693 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
445732 |
1 |
|
|
T20 |
2 |
|
T26 |
27 |
|
T27 |
151 |
| auto[1] |
auto[0] |
auto[1] |
406929 |
1 |
|
|
T20 |
12 |
|
T26 |
44 |
|
T27 |
150 |
| auto[1] |
auto[1] |
auto[0] |
439507 |
1 |
|
|
T20 |
3 |
|
T26 |
42 |
|
T27 |
173 |
| auto[1] |
auto[1] |
auto[1] |
404548 |
1 |
|
|
T26 |
54 |
|
T27 |
219 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |