Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3528123 |
1 |
|
|
T20 |
89 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1685094 |
1 |
|
|
T20 |
37 |
|
T26 |
208 |
|
T27 |
934 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997888 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215329 |
1 |
|
|
T26 |
6 |
|
T27 |
191 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3526042 |
1 |
|
|
T20 |
110 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1687175 |
1 |
|
|
T20 |
16 |
|
T26 |
133 |
|
T27 |
962 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
741622 |
1 |
|
|
T20 |
10 |
|
T26 |
75 |
|
T27 |
337 |
| auto[1] |
auto[0] |
auto[1] |
109281 |
1 |
|
|
T26 |
4 |
|
T27 |
87 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
730224 |
1 |
|
|
T20 |
6 |
|
T26 |
52 |
|
T27 |
434 |
| auto[1] |
auto[1] |
auto[1] |
106048 |
1 |
|
|
T26 |
2 |
|
T27 |
104 |
|
T2 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |