Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3517170 |
1 |
|
|
T20 |
71 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1696047 |
1 |
|
|
T20 |
55 |
|
T26 |
147 |
|
T27 |
747 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4996937 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216280 |
1 |
|
|
T26 |
8 |
|
T27 |
195 |
|
T2 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523661 |
1 |
|
|
T20 |
100 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1689556 |
1 |
|
|
T20 |
26 |
|
T26 |
146 |
|
T27 |
976 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
736938 |
1 |
|
|
T20 |
17 |
|
T26 |
81 |
|
T27 |
459 |
| auto[1] |
auto[0] |
auto[1] |
108287 |
1 |
|
|
T26 |
4 |
|
T27 |
114 |
|
T2 |
11 |
| auto[1] |
auto[1] |
auto[0] |
736338 |
1 |
|
|
T20 |
9 |
|
T26 |
57 |
|
T27 |
322 |
| auto[1] |
auto[1] |
auto[1] |
107993 |
1 |
|
|
T26 |
4 |
|
T27 |
81 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |