Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3514668 |
1 |
|
|
T20 |
72 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1698549 |
1 |
|
|
T20 |
54 |
|
T26 |
197 |
|
T27 |
914 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997877 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215340 |
1 |
|
|
T20 |
1 |
|
T26 |
12 |
|
T27 |
157 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3526512 |
1 |
|
|
T20 |
66 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1686705 |
1 |
|
|
T20 |
60 |
|
T26 |
172 |
|
T27 |
820 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
739817 |
1 |
|
|
T20 |
29 |
|
T26 |
63 |
|
T27 |
296 |
| auto[1] |
auto[0] |
auto[1] |
108230 |
1 |
|
|
T20 |
1 |
|
T26 |
4 |
|
T27 |
70 |
| auto[1] |
auto[1] |
auto[0] |
731548 |
1 |
|
|
T20 |
30 |
|
T26 |
97 |
|
T27 |
367 |
| auto[1] |
auto[1] |
auto[1] |
107110 |
1 |
|
|
T26 |
8 |
|
T27 |
87 |
|
T2 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |