Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3535663 |
1 |
|
|
T20 |
67 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1677554 |
1 |
|
|
T20 |
59 |
|
T26 |
221 |
|
T27 |
1048 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4995823 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
217394 |
1 |
|
|
T26 |
9 |
|
T27 |
178 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3510968 |
1 |
|
|
T20 |
110 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1702249 |
1 |
|
|
T20 |
16 |
|
T26 |
196 |
|
T27 |
909 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
754224 |
1 |
|
|
T20 |
3 |
|
T26 |
68 |
|
T27 |
204 |
| auto[1] |
auto[0] |
auto[1] |
110560 |
1 |
|
|
T26 |
3 |
|
T27 |
47 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
730631 |
1 |
|
|
T20 |
13 |
|
T26 |
119 |
|
T27 |
527 |
| auto[1] |
auto[1] |
auto[1] |
106834 |
1 |
|
|
T26 |
6 |
|
T27 |
131 |
|
T2 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |