Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3521294 |
1 |
|
|
T20 |
84 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1691923 |
1 |
|
|
T20 |
42 |
|
T26 |
155 |
|
T27 |
928 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4996573 |
1 |
|
|
T20 |
125 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
216644 |
1 |
|
|
T20 |
1 |
|
T26 |
9 |
|
T27 |
166 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3522589 |
1 |
|
|
T20 |
85 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690628 |
1 |
|
|
T20 |
41 |
|
T26 |
155 |
|
T27 |
859 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
735447 |
1 |
|
|
T20 |
22 |
|
T26 |
78 |
|
T27 |
261 |
| auto[1] |
auto[0] |
auto[1] |
107753 |
1 |
|
|
T20 |
1 |
|
T26 |
6 |
|
T27 |
52 |
| auto[1] |
auto[1] |
auto[0] |
738537 |
1 |
|
|
T20 |
18 |
|
T26 |
68 |
|
T27 |
432 |
| auto[1] |
auto[1] |
auto[1] |
108891 |
1 |
|
|
T26 |
3 |
|
T27 |
114 |
|
T2 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |