Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3539409 |
1 |
|
|
T20 |
89 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1673808 |
1 |
|
|
T20 |
37 |
|
T26 |
150 |
|
T27 |
986 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4997824 |
1 |
|
|
T20 |
126 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
215393 |
1 |
|
|
T26 |
12 |
|
T27 |
207 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
3523173 |
1 |
|
|
T20 |
94 |
|
T21 |
87 |
|
T22 |
230 |
| auto[1] |
1690044 |
1 |
|
|
T20 |
32 |
|
T26 |
169 |
|
T27 |
1044 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
744504 |
1 |
|
|
T20 |
22 |
|
T26 |
94 |
|
T27 |
348 |
| auto[1] |
auto[0] |
auto[1] |
109073 |
1 |
|
|
T26 |
9 |
|
T27 |
83 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[0] |
730147 |
1 |
|
|
T20 |
10 |
|
T26 |
63 |
|
T27 |
489 |
| auto[1] |
auto[1] |
auto[1] |
106320 |
1 |
|
|
T26 |
3 |
|
T27 |
124 |
|
T2 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |