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Group Instance : intr_event_lvlhigh_pin9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvlhigh_pin9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvlhigh_pin9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvlhigh_pin9
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin0
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin1
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin10
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin10

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin10
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin10
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin11
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin11

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin11
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin11
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin12
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin12

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin12
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin12
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin13
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin13

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin13
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin13
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin14
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin14

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin14
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin14
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin15
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin15

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin15
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin15
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin16
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin16

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin16
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin16
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin17
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin17

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin17
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin17
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin18
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin18

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin18
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin18
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0



Group Instance : intr_event_lvllow_pin19
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance intr_event_lvllow_pin19

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin19
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin19
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0

Go back
Group Instances:
intr_event_lvlhigh_pin9
intr_event_lvllow_pin0
intr_event_lvllow_pin1
intr_event_lvllow_pin10
intr_event_lvllow_pin11
intr_event_lvllow_pin12
intr_event_lvllow_pin13
intr_event_lvllow_pin14
intr_event_lvllow_pin15
intr_event_lvllow_pin16
intr_event_lvllow_pin17
intr_event_lvllow_pin18
intr_event_lvllow_pin19

Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3520188 1 T20 88 T21 87 T22 230
auto[1] 1693029 1 T20 38 T26 118 T27 881



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4400860 1 T20 105 T21 87 T22 230
auto[1] 812357 1 T20 21 T26 83 T27 477



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3512044 1 T20 95 T21 87 T22 230
auto[1] 1701173 1 T20 31 T26 204 T27 1009



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 443611 1 T20 4 T26 69 T27 218
auto[1] auto[0] auto[1] 406828 1 T20 15 T26 62 T27 180
auto[1] auto[1] auto[0] 445205 1 T20 6 T26 52 T27 314
auto[1] auto[1] auto[1] 405529 1 T20 6 T26 21 T27 297


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3533417 1 T20 96 T21 87 T22 230
auto[1] 1679800 1 T20 30 T26 178 T27 743



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4332133 1 T20 125 T21 87 T22 230
auto[1] 881084 1 T20 1 T26 120 T27 422



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3528635 1 T20 115 T21 87 T22 230
auto[1] 1684582 1 T20 11 T26 242 T27 854



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 405365 1 T20 10 T26 61 T27 234
auto[1] auto[0] auto[1] 444552 1 T26 40 T27 258 T1 2
auto[1] auto[1] auto[0] 398133 1 T26 61 T27 198 T2 141
auto[1] auto[1] auto[1] 436532 1 T20 1 T26 80 T27 164


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3540943 1 T20 73 T21 87 T22 230
auto[1] 1672274 1 T20 53 T26 173 T27 963



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4333307 1 T20 110 T21 87 T22 230
auto[1] 879910 1 T20 16 T26 115 T27 368



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3527278 1 T20 90 T21 87 T22 230
auto[1] 1685939 1 T20 36 T26 199 T27 705



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 407065 1 T20 15 T26 34 T27 125
auto[1] auto[0] auto[1] 442576 1 T20 9 T26 68 T27 158
auto[1] auto[1] auto[0] 398964 1 T20 5 T26 50 T27 212
auto[1] auto[1] auto[1] 437334 1 T20 7 T26 47 T27 210


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3532848 1 T20 94 T21 87 T22 230
auto[1] 1680369 1 T20 32 T26 154 T27 852



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4334214 1 T20 112 T21 87 T22 230
auto[1] 879003 1 T20 14 T26 104 T27 529



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3532280 1 T20 77 T21 87 T22 230
auto[1] 1680937 1 T20 49 T26 162 T27 1040



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 404619 1 T20 28 T26 25 T27 292
auto[1] auto[0] auto[1] 448138 1 T20 11 T26 52 T27 289
auto[1] auto[1] auto[0] 397315 1 T20 7 T26 33 T27 219
auto[1] auto[1] auto[1] 430865 1 T20 3 T26 52 T27 240


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3515832 1 T20 84 T21 87 T22 230
auto[1] 1697385 1 T20 42 T26 138 T27 861



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4326992 1 T20 112 T21 87 T22 230
auto[1] 886225 1 T20 14 T26 79 T27 481



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3519519 1 T20 98 T21 87 T22 230
auto[1] 1693698 1 T20 28 T26 175 T27 928



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 404309 1 T20 12 T26 47 T27 215
auto[1] auto[0] auto[1] 441405 1 T20 5 T26 55 T27 252
auto[1] auto[1] auto[0] 403164 1 T20 2 T26 49 T27 232
auto[1] auto[1] auto[1] 444820 1 T20 9 T26 24 T27 229


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3511855 1 T20 84 T21 87 T22 230
auto[1] 1701362 1 T20 42 T26 191 T27 938



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4332658 1 T20 119 T21 87 T22 230
auto[1] 880559 1 T20 7 T26 85 T27 406



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3525051 1 T20 103 T21 87 T22 230
auto[1] 1688166 1 T20 23 T26 169 T27 818



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 404123 1 T20 9 T26 43 T27 204
auto[1] auto[0] auto[1] 439459 1 T20 5 T26 27 T27 211
auto[1] auto[1] auto[0] 403484 1 T20 7 T26 41 T27 208
auto[1] auto[1] auto[1] 441100 1 T20 2 T26 58 T27 195


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3511173 1 T20 102 T21 87 T22 230
auto[1] 1702044 1 T20 24 T26 235 T27 900



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4327962 1 T20 102 T21 87 T22 230
auto[1] 885255 1 T20 24 T26 101 T27 471



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3520201 1 T20 100 T21 87 T22 230
auto[1] 1693016 1 T20 26 T26 152 T27 868



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 400946 1 T20 1 T26 17 T27 148
auto[1] auto[0] auto[1] 436656 1 T20 18 T26 27 T27 209
auto[1] auto[1] auto[0] 406815 1 T20 1 T26 34 T27 249
auto[1] auto[1] auto[1] 448599 1 T20 6 T26 74 T27 262


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3523037 1 T20 85 T21 87 T22 230
auto[1] 1690180 1 T20 41 T26 216 T27 988



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4326714 1 T20 110 T21 87 T22 230
auto[1] 886503 1 T20 16 T26 95 T27 274



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3520099 1 T20 84 T21 87 T22 230
auto[1] 1693118 1 T20 42 T26 172 T27 537



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 402770 1 T20 16 T26 33 T27 113
auto[1] auto[0] auto[1] 447169 1 T20 16 T26 47 T27 107
auto[1] auto[1] auto[0] 403845 1 T20 10 T26 44 T27 150
auto[1] auto[1] auto[1] 439334 1 T26 48 T27 167 T1 3


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3516230 1 T20 101 T21 87 T22 230
auto[1] 1696987 1 T20 25 T26 192 T27 987



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4332843 1 T20 106 T21 87 T22 230
auto[1] 880374 1 T20 20 T26 118 T27 394



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3529367 1 T20 101 T21 87 T22 230
auto[1] 1683850 1 T20 25 T26 176 T27 794



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 401073 1 T20 5 T26 27 T27 115
auto[1] auto[0] auto[1] 439235 1 T20 14 T26 52 T27 104
auto[1] auto[1] auto[0] 402403 1 T26 31 T27 285 T1 1
auto[1] auto[1] auto[1] 441139 1 T20 6 T26 66 T27 290


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3524937 1 T20 65 T21 87 T22 230
auto[1] 1688280 1 T20 61 T26 224 T27 705



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4327259 1 T20 121 T21 87 T22 230
auto[1] 885958 1 T20 5 T26 54 T27 420



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3519076 1 T20 90 T21 87 T22 230
auto[1] 1694141 1 T20 36 T26 144 T27 807



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 405996 1 T20 17 T26 37 T27 253
auto[1] auto[0] auto[1] 448288 1 T20 1 T26 24 T27 279
auto[1] auto[1] auto[0] 402187 1 T20 14 T26 53 T27 134
auto[1] auto[1] auto[1] 437670 1 T20 4 T26 30 T27 141


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3516784 1 T20 72 T21 87 T22 230
auto[1] 1696433 1 T20 54 T26 195 T27 592



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4331642 1 T20 120 T21 87 T22 230
auto[1] 881575 1 T20 6 T26 57 T27 426



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3529416 1 T20 102 T21 87 T22 230
auto[1] 1683801 1 T20 24 T26 155 T27 910



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 400339 1 T20 6 T26 27 T27 322
auto[1] auto[0] auto[1] 443751 1 T20 1 T26 24 T27 287
auto[1] auto[1] auto[0] 401887 1 T20 12 T26 71 T27 162
auto[1] auto[1] auto[1] 437824 1 T20 5 T26 33 T27 139


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3540367 1 T20 81 T21 87 T22 230
auto[1] 1672850 1 T20 45 T26 119 T27 982



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4319222 1 T20 112 T21 87 T22 230
auto[1] 893995 1 T20 14 T26 82 T27 357



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3506820 1 T20 102 T21 87 T22 230
auto[1] 1706397 1 T20 24 T26 198 T27 643



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 410663 1 T20 3 T26 92 T27 130
auto[1] auto[0] auto[1] 455189 1 T20 13 T26 59 T27 156
auto[1] auto[1] auto[0] 401739 1 T20 7 T26 24 T27 156
auto[1] auto[1] auto[1] 438806 1 T20 1 T26 23 T27 201


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3527120 1 T20 79 T21 87 T22 230
auto[1] 1686097 1 T20 47 T26 105 T27 955



Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4326879 1 T20 103 T21 87 T22 230
auto[1] 886338 1 T20 23 T26 67 T27 426



Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3517153 1 T20 91 T21 87 T22 230
auto[1] 1696064 1 T20 35 T26 134 T27 826



Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 407611 1 T20 5 T26 43 T27 209
auto[1] auto[0] auto[1] 446049 1 T20 16 T26 53 T27 205
auto[1] auto[1] auto[0] 402115 1 T20 7 T26 24 T27 191
auto[1] auto[1] auto[1] 440289 1 T20 7 T26 14 T27 221


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

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