Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1780517	1			T33	1		T34	1		T35	1
all_pins[1]	1780517	1			T33	1		T34	1		T35	1
all_pins[2]	1780517	1			T33	1		T34	1		T35	1
all_pins[3]	1780517	1			T33	1		T34	1		T35	1
all_pins[4]	1780517	1			T33	1		T34	1		T35	1
all_pins[5]	1780517	1			T33	1		T34	1		T35	1
all_pins[6]	1780517	1			T33	1		T34	1		T35	1
all_pins[7]	1780517	1			T33	1		T34	1		T35	1
all_pins[8]	1780517	1			T33	1		T34	1		T35	1
all_pins[9]	1780517	1			T33	1		T34	1		T35	1
all_pins[10]	1780517	1			T33	1		T34	1		T35	1
all_pins[11]	1780517	1			T33	1		T34	1		T35	1
all_pins[12]	1780517	1			T33	1		T34	1		T35	1
all_pins[13]	1780517	1			T33	1		T34	1		T35	1
all_pins[14]	1780517	1			T33	1		T34	1		T35	1
all_pins[15]	1780517	1			T33	1		T34	1		T35	1
all_pins[16]	1780517	1			T33	1		T34	1		T35	1
all_pins[17]	1780517	1			T33	1		T34	1		T35	1
all_pins[18]	1780517	1			T33	1		T34	1		T35	1
all_pins[19]	1780517	1			T33	1		T34	1		T35	1
all_pins[20]	1780517	1			T33	1		T34	1		T35	1
all_pins[21]	1780517	1			T33	1		T34	1		T35	1
all_pins[22]	1780517	1			T33	1		T34	1		T35	1
all_pins[23]	1780517	1			T33	1		T34	1		T35	1
all_pins[24]	1780517	1			T33	1		T34	1		T35	1
all_pins[25]	1780517	1			T33	1		T34	1		T35	1
all_pins[26]	1780517	1			T33	1		T34	1		T35	1
all_pins[27]	1780517	1			T33	1		T34	1		T35	1
all_pins[28]	1780517	1			T33	1		T34	1		T35	1
all_pins[29]	1780517	1			T33	1		T34	1		T35	1
all_pins[30]	1780517	1			T33	1		T34	1		T35	1
all_pins[31]	1780517	1			T33	1		T34	1		T35	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	35419880	1			T33	32		T34	32		T35	32
values[0x1]	21556664	1			T38	2522		T39	635		T20	390
transitions[0x0=>0x1]	12901341	1			T38	1544		T39	328		T20	295
transitions[0x1=>0x0]	12901188	1			T38	1544		T39	327		T20	295

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1102689	1			T33	1		T34	1		T35	1
all_pins[0]	values[0x1]	677828	1			T38	85		T39	19		T20	19
all_pins[0]	transitions[0x0=>0x1]	419844	1			T38	58		T39	9		T20	18
all_pins[0]	transitions[0x1=>0x0]	414636	1			T38	38		T39	11		T20	7
all_pins[1]	values[0x0]	1108527	1			T33	1		T34	1		T35	1
all_pins[1]	values[0x1]	671990	1			T38	67		T39	17		T20	16
all_pins[1]	transitions[0x0=>0x1]	400613	1			T38	47		T39	11		T20	11
all_pins[1]	transitions[0x1=>0x0]	406451	1			T38	65		T39	13		T20	14
all_pins[2]	values[0x0]	1104220	1			T33	1		T34	1		T35	1
all_pins[2]	values[0x1]	676297	1			T38	95		T39	19		T20	6
all_pins[2]	transitions[0x0=>0x1]	403403	1			T38	58		T39	12		T20	3
all_pins[2]	transitions[0x1=>0x0]	399096	1			T38	30		T39	10		T20	13
all_pins[3]	values[0x0]	1103794	1			T33	1		T34	1		T35	1
all_pins[3]	values[0x1]	676723	1			T38	66		T39	20		T20	12
all_pins[3]	transitions[0x0=>0x1]	401941	1			T38	44		T39	11		T20	8
all_pins[3]	transitions[0x1=>0x0]	401515	1			T38	73		T39	10		T20	2
all_pins[4]	values[0x0]	1102036	1			T33	1		T34	1		T35	1
all_pins[4]	values[0x1]	678481	1			T38	81		T39	22		T20	10
all_pins[4]	transitions[0x0=>0x1]	404690	1			T38	48		T39	13		T20	4
all_pins[4]	transitions[0x1=>0x0]	402932	1			T38	33		T39	11		T20	6
all_pins[5]	values[0x0]	1107268	1			T33	1		T34	1		T35	1
all_pins[5]	values[0x1]	673249	1			T38	84		T39	16		T20	18
all_pins[5]	transitions[0x0=>0x1]	400790	1			T38	53		T39	6		T20	16
all_pins[5]	transitions[0x1=>0x0]	406022	1			T38	50		T39	12		T20	8
all_pins[6]	values[0x0]	1109068	1			T33	1		T34	1		T35	1
all_pins[6]	values[0x1]	671449	1			T38	67		T39	24		T20	19
all_pins[6]	transitions[0x0=>0x1]	402036	1			T38	39		T39	14		T20	8
all_pins[6]	transitions[0x1=>0x0]	403836	1			T38	56		T39	6		T20	7
all_pins[7]	values[0x0]	1102601	1			T33	1		T34	1		T35	1
all_pins[7]	values[0x1]	677916	1			T38	92		T39	17		T20	11
all_pins[7]	transitions[0x0=>0x1]	407091	1			T38	63		T39	9		T20	10
all_pins[7]	transitions[0x1=>0x0]	400624	1			T38	38		T39	16		T20	18
all_pins[8]	values[0x0]	1105254	1			T33	1		T34	1		T35	1
all_pins[8]	values[0x1]	675263	1			T38	70		T39	20		T20	14
all_pins[8]	transitions[0x0=>0x1]	401971	1			T38	48		T39	13		T20	9
all_pins[8]	transitions[0x1=>0x0]	404624	1			T38	70		T39	10		T20	6
all_pins[9]	values[0x0]	1110144	1			T33	1		T34	1		T35	1
all_pins[9]	values[0x1]	670373	1			T38	58		T39	17		T20	8
all_pins[9]	transitions[0x0=>0x1]	400403	1			T38	41		T39	9		T20	7
all_pins[9]	transitions[0x1=>0x0]	405293	1			T38	53		T39	12		T20	13
all_pins[10]	values[0x0]	1106296	1			T33	1		T34	1		T35	1
all_pins[10]	values[0x1]	674221	1			T38	80		T39	20		T20	10
all_pins[10]	transitions[0x0=>0x1]	403916	1			T38	64		T39	12		T20	8
all_pins[10]	transitions[0x1=>0x0]	400068	1			T38	42		T39	9		T20	6
all_pins[11]	values[0x0]	1108082	1			T33	1		T34	1		T35	1
all_pins[11]	values[0x1]	672435	1			T38	86		T39	24		T20	16
all_pins[11]	transitions[0x0=>0x1]	402334	1			T38	50		T39	13		T20	12
all_pins[11]	transitions[0x1=>0x0]	404120	1			T38	44		T39	9		T20	6
all_pins[12]	values[0x0]	1105769	1			T33	1		T34	1		T35	1
all_pins[12]	values[0x1]	674748	1			T38	93		T39	23		T20	7
all_pins[12]	transitions[0x0=>0x1]	402952	1			T38	56		T39	9		T20	6
all_pins[12]	transitions[0x1=>0x0]	400639	1			T38	49		T39	10		T20	15
all_pins[13]	values[0x0]	1110603	1			T33	1		T34	1		T35	1
all_pins[13]	values[0x1]	669914	1			T38	54		T39	13		T20	12
all_pins[13]	transitions[0x0=>0x1]	399778	1			T38	27		T39	7		T20	11
all_pins[13]	transitions[0x1=>0x0]	404612	1			T38	66		T39	17		T20	6
all_pins[14]	values[0x0]	1104855	1			T33	1		T34	1		T35	1
all_pins[14]	values[0x1]	675662	1			T38	89		T39	18		T20	19
all_pins[14]	transitions[0x0=>0x1]	406156	1			T38	66		T39	11		T20	19
all_pins[14]	transitions[0x1=>0x0]	400408	1			T38	31		T39	6		T20	12
all_pins[15]	values[0x0]	1106790	1			T33	1		T34	1		T35	1
all_pins[15]	values[0x1]	673727	1			T38	102		T39	21		T20	4
all_pins[15]	transitions[0x0=>0x1]	401963	1			T38	56		T39	9		T20	2
all_pins[15]	transitions[0x1=>0x0]	403898	1			T38	43		T39	6		T20	17
all_pins[16]	values[0x0]	1110087	1			T33	1		T34	1		T35	1
all_pins[16]	values[0x1]	670430	1			T38	77		T39	21		T20	5
all_pins[16]	transitions[0x0=>0x1]	400957	1			T38	45		T39	11		T20	5
all_pins[16]	transitions[0x1=>0x0]	404254	1			T38	70		T39	11		T20	4
all_pins[17]	values[0x0]	1105364	1			T33	1		T34	1		T35	1
all_pins[17]	values[0x1]	675153	1			T38	94		T39	20		T20	17
all_pins[17]	transitions[0x0=>0x1]	405838	1			T38	59		T39	11		T20	13
all_pins[17]	transitions[0x1=>0x0]	401115	1			T38	42		T39	12		T20	1
all_pins[18]	values[0x0]	1105741	1			T33	1		T34	1		T35	1
all_pins[18]	values[0x1]	674776	1			T38	65		T39	19		T20	12
all_pins[18]	transitions[0x0=>0x1]	402968	1			T38	33		T39	8		T20	8
all_pins[18]	transitions[0x1=>0x0]	403345	1			T38	62		T39	9		T20	13
all_pins[19]	values[0x0]	1107891	1			T33	1		T34	1		T35	1
all_pins[19]	values[0x1]	672626	1			T38	60		T39	19		T20	16
all_pins[19]	transitions[0x0=>0x1]	402064	1			T38	36		T39	8		T20	16
all_pins[19]	transitions[0x1=>0x0]	404214	1			T38	41		T39	8		T20	12
all_pins[20]	values[0x0]	1112497	1			T33	1		T34	1		T35	1
all_pins[20]	values[0x1]	668020	1			T38	81		T39	18		T20	19
all_pins[20]	transitions[0x0=>0x1]	399472	1			T38	51		T39	6		T20	8
all_pins[20]	transitions[0x1=>0x0]	404078	1			T38	30		T39	7		T20	5
all_pins[21]	values[0x0]	1105736	1			T33	1		T34	1		T35	1
all_pins[21]	values[0x1]	674781	1			T38	67		T39	17		T20	16
all_pins[21]	transitions[0x0=>0x1]	405082	1			T38	25		T39	9		T20	11
all_pins[21]	transitions[0x1=>0x0]	398321	1			T38	39		T39	10		T20	14
all_pins[22]	values[0x0]	1107227	1			T33	1		T34	1		T35	1
all_pins[22]	values[0x1]	673290	1			T38	67		T39	14		T20	19
all_pins[22]	transitions[0x0=>0x1]	402630	1			T38	52		T39	6		T20	19
all_pins[22]	transitions[0x1=>0x0]	404121	1			T38	52		T39	9		T20	16
all_pins[23]	values[0x0]	1106099	1			T33	1		T34	1		T35	1
all_pins[23]	values[0x1]	674418	1			T38	64		T39	25		T20	11
all_pins[23]	transitions[0x0=>0x1]	402380	1			T38	45		T39	16		T20	5
all_pins[23]	transitions[0x1=>0x0]	401252	1			T38	48		T39	5		T20	13
all_pins[24]	values[0x0]	1108154	1			T33	1		T34	1		T35	1
all_pins[24]	values[0x1]	672363	1			T38	65		T39	22		T20	14
all_pins[24]	transitions[0x0=>0x1]	401380	1			T38	41		T39	9		T20	10
all_pins[24]	transitions[0x1=>0x0]	403435	1			T38	40		T39	12		T20	7
all_pins[25]	values[0x0]	1111765	1			T33	1		T34	1		T35	1
all_pins[25]	values[0x1]	668752	1			T38	111		T39	21		T20	13
all_pins[25]	transitions[0x0=>0x1]	400247	1			T38	71		T39	12		T20	6
all_pins[25]	transitions[0x1=>0x0]	403858	1			T38	25		T39	13		T20	7
all_pins[26]	values[0x0]	1108318	1			T33	1		T34	1		T35	1
all_pins[26]	values[0x1]	672199	1			T38	101		T39	20		T20	1
all_pins[26]	transitions[0x0=>0x1]	402352	1			T38	50		T39	8		T20	1
all_pins[26]	transitions[0x1=>0x0]	398905	1			T38	60		T39	9		T20	13
all_pins[27]	values[0x0]	1107535	1			T33	1		T34	1		T35	1
all_pins[27]	values[0x1]	672982	1			T38	77		T39	24		T20	5
all_pins[27]	transitions[0x0=>0x1]	402330	1			T38	42		T39	14		T20	5
all_pins[27]	transitions[0x1=>0x0]	401547	1			T38	66		T39	10		T20	1
all_pins[28]	values[0x0]	1109413	1			T33	1		T34	1		T35	1
all_pins[28]	values[0x1]	671104	1			T38	88		T39	23		T20	11
all_pins[28]	transitions[0x0=>0x1]	400947	1			T38	59		T39	8		T20	9
all_pins[28]	transitions[0x1=>0x0]	402825	1			T38	48		T39	9		T20	3
all_pins[29]	values[0x0]	1104552	1			T33	1		T34	1		T35	1
all_pins[29]	values[0x1]	675965	1			T38	77		T39	21		T20	4
all_pins[29]	transitions[0x0=>0x1]	406912	1			T38	41		T39	10		T20	4
all_pins[29]	transitions[0x1=>0x0]	402051	1			T38	52		T39	12		T20	11
all_pins[30]	values[0x0]	1103761	1			T33	1		T34	1		T35	1
all_pins[30]	values[0x1]	676756	1			T38	94		T39	19		T20	18
all_pins[30]	transitions[0x0=>0x1]	404627	1			T38	45		T39	11		T20	15
all_pins[30]	transitions[0x1=>0x0]	403836	1			T38	28		T39	13		T20	1
all_pins[31]	values[0x0]	1107744	1			T33	1		T34	1		T35	1
all_pins[31]	values[0x1]	672773	1			T38	65		T39	22		T20	8
all_pins[31]	transitions[0x0=>0x1]	401274	1			T38	31		T39	13		T20	8
all_pins[31]	transitions[0x1=>0x0]	405257	1			T38	60		T39	10		T20	18