Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7177441	1			T33	204		T34	230		T35	242
all_values[1]	7177441	1			T33	204		T34	230		T35	242
all_values[2]	7177441	1			T33	204		T34	230		T35	242
all_values[3]	7177441	1			T33	204		T34	230		T35	242
all_values[4]	7177441	1			T33	204		T34	230		T35	242
all_values[5]	7177441	1			T33	204		T34	230		T35	242
all_values[6]	7177441	1			T33	204		T34	230		T35	242
all_values[7]	7177441	1			T33	204		T34	230		T35	242
all_values[8]	7177441	1			T33	204		T34	230		T35	242
all_values[9]	7177441	1			T33	204		T34	230		T35	242
all_values[10]	7177441	1			T33	204		T34	230		T35	242
all_values[11]	7177441	1			T33	204		T34	230		T35	242
all_values[12]	7177441	1			T33	204		T34	230		T35	242
all_values[13]	7177441	1			T33	204		T34	230		T35	242
all_values[14]	7177441	1			T33	204		T34	230		T35	242
all_values[15]	7177441	1			T33	204		T34	230		T35	242
all_values[16]	7177441	1			T33	204		T34	230		T35	242
all_values[17]	7177441	1			T33	204		T34	230		T35	242
all_values[18]	7177441	1			T33	204		T34	230		T35	242
all_values[19]	7177441	1			T33	204		T34	230		T35	242
all_values[20]	7177441	1			T33	204		T34	230		T35	242
all_values[21]	7177441	1			T33	204		T34	230		T35	242
all_values[22]	7177441	1			T33	204		T34	230		T35	242
all_values[23]	7177441	1			T33	204		T34	230		T35	242
all_values[24]	7177441	1			T33	204		T34	230		T35	242
all_values[25]	7177441	1			T33	204		T34	230		T35	242
all_values[26]	7177441	1			T33	204		T34	230		T35	242
all_values[27]	7177441	1			T33	204		T34	230		T35	242
all_values[28]	7177441	1			T33	204		T34	230		T35	242
all_values[29]	7177441	1			T33	204		T34	230		T35	242
all_values[30]	7177441	1			T33	204		T34	230		T35	242
all_values[31]	7177441	1			T33	204		T34	230		T35	242

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152226587

1

T33

6528

T34

7360

T35

7744

auto[1]

77451525

1

T38

5656

T20

1131

T22

34729

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89937951

1

T33

6528

T34

7360

T35

7744

auto[1]

139740161

1

T38

10266

T20

1144

T22

66224

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227536548

1

T33

6528

T34

7360

T35

7744

auto[1]

2141564

1

T20

99

T23

1149

T48

205

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2565013	1			T33	204		T34	230		T35	242
all_values[0]	auto[0]	auto[0]	auto[1]	2149301	1			T38	132		T20	15		T22	1234
all_values[0]	auto[0]	auto[1]	auto[0]	242942	1			T38	37		T20	23		T22	143
all_values[0]	auto[0]	auto[1]	auto[1]	2153350	1			T38	167		T20	27		T22	797
all_values[0]	auto[1]	auto[0]	auto[1]	33523	1			T20	2		T23	22		T48	4
all_values[0]	auto[1]	auto[1]	auto[1]	33312	1			T20	2		T23	19		T48	3
all_values[1]	auto[0]	auto[0]	auto[0]	2568387	1			T33	204		T34	230		T35	242
all_values[1]	auto[0]	auto[0]	auto[1]	2156546	1			T38	189		T20	21		T22	932
all_values[1]	auto[0]	auto[1]	auto[0]	242142	1			T38	28		T20	18		T22	133
all_values[1]	auto[0]	auto[1]	auto[1]	2143771	1			T38	136		T20	17		T22	1153
all_values[1]	auto[1]	auto[0]	auto[1]	33627	1			T23	14		T48	9		T112	28
all_values[1]	auto[1]	auto[1]	auto[1]	32968	1			T20	3		T23	15		T112	17
all_values[2]	auto[0]	auto[0]	auto[0]	2562821	1			T33	204		T34	230		T35	242
all_values[2]	auto[0]	auto[0]	auto[1]	2164993	1			T38	188		T20	13		T22	969
all_values[2]	auto[0]	auto[1]	auto[0]	243448	1			T38	14		T20	15		T22	124
all_values[2]	auto[0]	auto[1]	auto[1]	2139564	1			T38	165		T20	8		T22	1044
all_values[2]	auto[1]	auto[0]	auto[1]	33569	1			T23	10		T48	8		T112	15
all_values[2]	auto[1]	auto[1]	auto[1]	33046	1			T20	1		T23	30		T48	2
all_values[3]	auto[0]	auto[0]	auto[0]	2566961	1			T33	204		T34	230		T35	242
all_values[3]	auto[0]	auto[0]	auto[1]	2149962	1			T38	153		T20	9		T22	1158
all_values[3]	auto[0]	auto[1]	auto[0]	242724	1			T38	61		T20	26		T22	90
all_values[3]	auto[0]	auto[1]	auto[1]	2150924	1			T38	124		T20	13		T22	932
all_values[3]	auto[1]	auto[0]	auto[1]	33645	1			T23	24		T48	5		T112	32
all_values[3]	auto[1]	auto[1]	auto[1]	33225	1			T20	4		T23	15		T48	3
all_values[4]	auto[0]	auto[0]	auto[0]	2564223	1			T33	204		T34	230		T35	242
all_values[4]	auto[0]	auto[0]	auto[1]	2145125	1			T38	187		T20	8		T22	1086
all_values[4]	auto[0]	auto[1]	auto[0]	242601	1			T38	14		T20	25		T22	86
all_values[4]	auto[0]	auto[1]	auto[1]	2158482	1			T38	158		T20	8		T22	986
all_values[4]	auto[1]	auto[0]	auto[1]	33694	1			T23	14		T48	6		T112	33
all_values[4]	auto[1]	auto[1]	auto[1]	33316	1			T20	3		T23	21		T112	8
all_values[5]	auto[0]	auto[0]	auto[0]	2567675	1			T33	204		T34	230		T35	242
all_values[5]	auto[0]	auto[0]	auto[1]	2157230	1			T38	124		T20	12		T22	1152
all_values[5]	auto[0]	auto[1]	auto[0]	244420	1			T38	36		T20	16		T22	50
all_values[5]	auto[0]	auto[1]	auto[1]	2140955	1			T38	168		T20	26		T22	961
all_values[5]	auto[1]	auto[0]	auto[1]	33598	1			T23	17		T48	2		T112	13
all_values[5]	auto[1]	auto[1]	auto[1]	33563	1			T20	2		T23	22		T48	1
all_values[6]	auto[0]	auto[0]	auto[0]	2568207	1			T33	204		T34	230		T35	242
all_values[6]	auto[0]	auto[0]	auto[1]	2163456	1			T38	181		T20	13		T22	1248
all_values[6]	auto[0]	auto[1]	auto[0]	246079	1			T38	40		T20	8		T22	51
all_values[6]	auto[0]	auto[1]	auto[1]	2132700	1			T38	129		T20	28		T22	805
all_values[6]	auto[1]	auto[0]	auto[1]	34162	1			T20	1		T23	14		T48	4
all_values[6]	auto[1]	auto[1]	auto[1]	32837	1			T20	1		T23	22		T48	1
all_values[7]	auto[0]	auto[0]	auto[0]	2565023	1			T33	204		T34	230		T35	242
all_values[7]	auto[0]	auto[0]	auto[1]	2140286	1			T38	142		T20	6		T22	1133
all_values[7]	auto[0]	auto[1]	auto[0]	245333	1			T38	27		T20	21		T22	136
all_values[7]	auto[0]	auto[1]	auto[1]	2159744	1			T38	176		T20	14		T22	835
all_values[7]	auto[1]	auto[0]	auto[1]	33699	1			T20	3		T23	19		T48	3
all_values[7]	auto[1]	auto[1]	auto[1]	33356	1			T20	2		T23	21		T48	3
all_values[8]	auto[0]	auto[0]	auto[0]	2570560	1			T33	204		T34	230		T35	242
all_values[8]	auto[0]	auto[0]	auto[1]	2145710	1			T38	202		T20	18		T22	926
all_values[8]	auto[0]	auto[1]	auto[0]	243175	1			T38	11		T20	9		T22	94
all_values[8]	auto[0]	auto[1]	auto[1]	2151170	1			T38	139		T20	23		T22	1182
all_values[8]	auto[1]	auto[0]	auto[1]	33659	1			T20	1		T23	17		T48	7
all_values[8]	auto[1]	auto[1]	auto[1]	33167	1			T23	14		T112	18		T21	3
all_values[9]	auto[0]	auto[0]	auto[0]	2568377	1			T33	204		T34	230		T35	242
all_values[9]	auto[0]	auto[0]	auto[1]	2149425	1			T38	224		T20	24		T22	1188
all_values[9]	auto[0]	auto[1]	auto[0]	246290	1			T38	18		T20	14		T22	41
all_values[9]	auto[0]	auto[1]	auto[1]	2146160	1			T38	109		T20	8		T22	904
all_values[9]	auto[1]	auto[0]	auto[1]	34137	1			T20	4		T23	12		T48	7
all_values[9]	auto[1]	auto[1]	auto[1]	33052	1			T20	2		T23	15		T112	17
all_values[10]	auto[0]	auto[0]	auto[0]	2565822	1			T33	204		T34	230		T35	242
all_values[10]	auto[0]	auto[0]	auto[1]	2162085	1			T38	132		T20	12		T22	1365
all_values[10]	auto[0]	auto[1]	auto[0]	243007	1			T38	48		T20	25		T22	48
all_values[10]	auto[0]	auto[1]	auto[1]	2139682	1			T38	162		T20	14		T22	707
all_values[10]	auto[1]	auto[0]	auto[1]	33775	1			T20	1		T23	14		T48	3
all_values[10]	auto[1]	auto[1]	auto[1]	33070	1			T20	1		T23	23		T112	18
all_values[11]	auto[0]	auto[0]	auto[0]	2571228	1			T33	204		T34	230		T35	242
all_values[11]	auto[0]	auto[0]	auto[1]	2152836	1			T38	176		T20	10		T22	1068
all_values[11]	auto[0]	auto[1]	auto[0]	244431	1			T38	20		T20	16		T22	87
all_values[11]	auto[0]	auto[1]	auto[1]	2142157	1			T38	148		T20	22		T22	980
all_values[11]	auto[1]	auto[0]	auto[1]	33461	1			T20	2		T23	20		T48	4
all_values[11]	auto[1]	auto[1]	auto[1]	33328	1			T20	1		T23	16		T48	2
all_values[12]	auto[0]	auto[0]	auto[0]	2562912	1			T33	204		T34	230		T35	242
all_values[12]	auto[0]	auto[0]	auto[1]	2141660	1			T38	169		T20	17		T22	936
all_values[12]	auto[0]	auto[1]	auto[0]	249458	1			T38	27		T20	19		T22	136
all_values[12]	auto[0]	auto[1]	auto[1]	2156315	1			T38	156		T20	9		T22	1136
all_values[12]	auto[1]	auto[0]	auto[1]	33314	1			T20	2		T23	11		T48	5
all_values[12]	auto[1]	auto[1]	auto[1]	33782	1			T20	2		T23	24		T48	3
all_values[13]	auto[0]	auto[0]	auto[0]	2567147	1			T33	204		T34	230		T35	242
all_values[13]	auto[0]	auto[0]	auto[1]	2153177	1			T38	215		T20	21		T22	1145
all_values[13]	auto[0]	auto[1]	auto[0]	249102	1			T38	26		T20	20		T22	111
all_values[13]	auto[0]	auto[1]	auto[1]	2141026	1			T38	105		T20	12		T22	873
all_values[13]	auto[1]	auto[0]	auto[1]	34029	1			T20	2		T23	19		T48	5
all_values[13]	auto[1]	auto[1]	auto[1]	32960	1			T20	2		T23	19		T48	1
all_values[14]	auto[0]	auto[0]	auto[0]	2564162	1			T33	204		T34	230		T35	242
all_values[14]	auto[0]	auto[0]	auto[1]	2148579	1			T38	159		T20	14		T22	939
all_values[14]	auto[0]	auto[1]	auto[0]	242957	1			T38	13		T20	25		T22	137
all_values[14]	auto[0]	auto[1]	auto[1]	2154825	1			T38	172		T20	18		T22	1093
all_values[14]	auto[1]	auto[0]	auto[1]	33509	1			T20	2		T23	21		T48	8
all_values[14]	auto[1]	auto[1]	auto[1]	33409	1			T20	3		T23	21		T112	23
all_values[15]	auto[0]	auto[0]	auto[0]	2563408	1			T33	204		T34	230		T35	242
all_values[15]	auto[0]	auto[0]	auto[1]	2145949	1			T38	170		T20	31		T22	773
all_values[15]	auto[0]	auto[1]	auto[0]	246669	1			T38	7		T20	13		T22	100
all_values[15]	auto[0]	auto[1]	auto[1]	2154565	1			T38	184		T20	6		T22	1287
all_values[15]	auto[1]	auto[0]	auto[1]	33551	1			T20	3		T23	18		T48	5
all_values[15]	auto[1]	auto[1]	auto[1]	33299	1			T23	18		T48	1		T112	21
all_values[16]	auto[0]	auto[0]	auto[0]	2571651	1			T33	204		T34	230		T35	242
all_values[16]	auto[0]	auto[0]	auto[1]	2174441	1			T38	146		T20	19		T22	908
all_values[16]	auto[0]	auto[1]	auto[0]	244786	1			T38	38		T20	30		T22	165
all_values[16]	auto[0]	auto[1]	auto[1]	2119731	1			T38	150		T20	4		T22	1153
all_values[16]	auto[1]	auto[0]	auto[1]	33842	1			T20	4		T23	20		T48	7
all_values[16]	auto[1]	auto[1]	auto[1]	32990	1			T20	2		T23	19		T112	17
all_values[17]	auto[0]	auto[0]	auto[0]	2565957	1			T33	204		T34	230		T35	242
all_values[17]	auto[0]	auto[0]	auto[1]	2170741	1			T38	161		T20	20		T22	1017
all_values[17]	auto[0]	auto[1]	auto[0]	240407	1			T38	26		T20	14		T22	86
all_values[17]	auto[0]	auto[1]	auto[1]	2133312	1			T38	166		T20	23		T22	1079
all_values[17]	auto[1]	auto[0]	auto[1]	33676	1			T20	1		T23	22		T48	3
all_values[17]	auto[1]	auto[1]	auto[1]	33348	1			T20	1		T23	12		T48	1
all_values[18]	auto[0]	auto[0]	auto[0]	2565196	1			T33	204		T34	230		T35	242
all_values[18]	auto[0]	auto[0]	auto[1]	2163668	1			T38	220		T20	20		T22	1519
all_values[18]	auto[0]	auto[1]	auto[0]	244234	1			T38	13		T20	11		T22	100
all_values[18]	auto[0]	auto[1]	auto[1]	2137191	1			T38	122		T20	17		T22	540
all_values[18]	auto[1]	auto[0]	auto[1]	33846	1			T20	1		T23	24		T48	8
all_values[18]	auto[1]	auto[1]	auto[1]	33306	1			T23	10		T112	28		T21	2
all_values[19]	auto[0]	auto[0]	auto[0]	2566593	1			T33	204		T34	230		T35	242
all_values[19]	auto[0]	auto[0]	auto[1]	2150123	1			T38	215		T20	21		T22	1502
all_values[19]	auto[0]	auto[1]	auto[0]	242841	1			T38	28		T20	13		T22	57
all_values[19]	auto[0]	auto[1]	auto[1]	2150882	1			T38	119		T20	16		T22	588
all_values[19]	auto[1]	auto[0]	auto[1]	33883	1			T20	1		T23	8		T48	6
all_values[19]	auto[1]	auto[1]	auto[1]	33119	1			T20	2		T23	24		T48	2
all_values[20]	auto[0]	auto[0]	auto[0]	2567902	1			T33	204		T34	230		T35	242
all_values[20]	auto[0]	auto[0]	auto[1]	2164944	1			T38	137		T20	14		T22	1032
all_values[20]	auto[0]	auto[1]	auto[0]	245949	1			T38	59		T20	18		T22	84
all_values[20]	auto[0]	auto[1]	auto[1]	2131881	1			T38	165		T20	24		T22	1030
all_values[20]	auto[1]	auto[0]	auto[1]	33934	1			T20	1		T23	21		T48	6
all_values[20]	auto[1]	auto[1]	auto[1]	32831	1			T20	2		T23	14		T48	1
all_values[21]	auto[0]	auto[0]	auto[0]	2565222	1			T33	204		T34	230		T35	242
all_values[21]	auto[0]	auto[0]	auto[1]	2154588	1			T38	199		T20	20		T22	974
all_values[21]	auto[0]	auto[1]	auto[0]	241330	1			T38	16		T20	24		T22	103
all_values[21]	auto[0]	auto[1]	auto[1]	2149170	1			T38	131		T20	17		T22	1049
all_values[21]	auto[1]	auto[0]	auto[1]	33539	1			T20	2		T23	17		T48	8
all_values[21]	auto[1]	auto[1]	auto[1]	33592	1			T20	2		T23	24		T48	1
all_values[22]	auto[0]	auto[0]	auto[0]	2569799	1			T33	204		T34	230		T35	242
all_values[22]	auto[0]	auto[0]	auto[1]	2160204	1			T38	216		T20	29		T22	1138
all_values[22]	auto[0]	auto[1]	auto[0]	242826	1			T38	21		T20	2		T22	71
all_values[22]	auto[0]	auto[1]	auto[1]	2137900	1			T38	117		T20	24		T22	977
all_values[22]	auto[1]	auto[0]	auto[1]	33559	1			T20	2		T23	15		T48	4
all_values[22]	auto[1]	auto[1]	auto[1]	33153	1			T20	3		T23	17		T48	2
all_values[23]	auto[0]	auto[0]	auto[0]	2564237	1			T33	204		T34	230		T35	242
all_values[23]	auto[0]	auto[0]	auto[1]	2154821	1			T38	146		T20	9		T22	1117
all_values[23]	auto[0]	auto[1]	auto[0]	240930	1			T38	53		T20	28		T22	44
all_values[23]	auto[0]	auto[1]	auto[1]	2150355	1			T38	126		T20	19		T22	974
all_values[23]	auto[1]	auto[0]	auto[1]	33968	1			T20	2		T23	27		T48	2
all_values[23]	auto[1]	auto[1]	auto[1]	33130	1			T20	1		T23	12		T48	2
all_values[24]	auto[0]	auto[0]	auto[0]	2566589	1			T33	204		T34	230		T35	242
all_values[24]	auto[0]	auto[0]	auto[1]	2153782	1			T38	219		T20	14		T22	831
all_values[24]	auto[0]	auto[1]	auto[0]	245149	1			T38	20		T20	25		T22	105
all_values[24]	auto[0]	auto[1]	auto[1]	2144710	1			T38	113		T20	17		T22	1162
all_values[24]	auto[1]	auto[0]	auto[1]	34242	1			T23	20		T48	5		T112	25
all_values[24]	auto[1]	auto[1]	auto[1]	32969	1			T20	2		T23	12		T112	22
all_values[25]	auto[0]	auto[0]	auto[0]	2565847	1			T33	204		T34	230		T35	242
all_values[25]	auto[0]	auto[0]	auto[1]	2171234	1			T38	136		T20	19		T22	1298
all_values[25]	auto[0]	auto[1]	auto[0]	246622	1			T38	17		T20	13		T22	49
all_values[25]	auto[0]	auto[1]	auto[1]	2126762	1			T38	206		T20	16		T22	840
all_values[25]	auto[1]	auto[0]	auto[1]	33681	1			T20	2		T23	19		T48	4
all_values[25]	auto[1]	auto[1]	auto[1]	33295	1			T20	2		T23	24		T48	1
all_values[26]	auto[0]	auto[0]	auto[0]	2567548	1			T33	204		T34	230		T35	242
all_values[26]	auto[0]	auto[0]	auto[1]	2156147	1			T38	138		T20	22		T22	1009
all_values[26]	auto[0]	auto[1]	auto[0]	247004	1			T38	21		T20	20		T22	59
all_values[26]	auto[0]	auto[1]	auto[1]	2139930	1			T38	200		T20	3		T22	1099
all_values[26]	auto[1]	auto[0]	auto[1]	33900	1			T20	1		T23	32		T48	6
all_values[26]	auto[1]	auto[1]	auto[1]	32912	1			T23	12		T48	1		T112	20
all_values[27]	auto[0]	auto[0]	auto[0]	2567036	1			T33	204		T34	230		T35	242
all_values[27]	auto[0]	auto[0]	auto[1]	2159444	1			T38	183		T20	20		T22	1166
all_values[27]	auto[0]	auto[1]	auto[0]	241600	1			T38	13		T20	25		T22	45
all_values[27]	auto[0]	auto[1]	auto[1]	2142356	1			T38	154		T20	7		T22	985
all_values[27]	auto[1]	auto[0]	auto[1]	33283	1			T20	1		T23	21		T48	5
all_values[27]	auto[1]	auto[1]	auto[1]	33722	1			T23	14		T48	2		T112	12
all_values[28]	auto[0]	auto[0]	auto[0]	2567062	1			T33	204		T34	230		T35	242
all_values[28]	auto[0]	auto[0]	auto[1]	2178932	1			T38	164		T20	18		T22	1033
all_values[28]	auto[0]	auto[1]	auto[0]	239831	1			T38	17		T20	23		T22	76
all_values[28]	auto[0]	auto[1]	auto[1]	2124652	1			T38	173		T20	11		T22	1101
all_values[28]	auto[1]	auto[0]	auto[1]	33647	1			T20	1		T23	13		T48	5
all_values[28]	auto[1]	auto[1]	auto[1]	33317	1			T20	1		T23	16		T112	16
all_values[29]	auto[0]	auto[0]	auto[0]	2569352	1			T33	204		T34	230		T35	242
all_values[29]	auto[0]	auto[0]	auto[1]	2156624	1			T38	132		T20	29		T22	1019
all_values[29]	auto[0]	auto[1]	auto[0]	242022	1			T38	31		T20	15		T22	60
all_values[29]	auto[0]	auto[1]	auto[1]	2142891	1			T38	151		T20	4		T22	1076
all_values[29]	auto[1]	auto[0]	auto[1]	33403	1			T20	4		T23	8		T48	3
all_values[29]	auto[1]	auto[1]	auto[1]	33149	1			T20	1		T23	30		T48	1
all_values[30]	auto[0]	auto[0]	auto[0]	2563806	1			T33	204		T34	230		T35	242
all_values[30]	auto[0]	auto[0]	auto[1]	2150235	1			T38	148		T20	11		T22	833
all_values[30]	auto[0]	auto[1]	auto[0]	245760	1			T38	34		T20	16		T22	118
all_values[30]	auto[0]	auto[1]	auto[1]	2150762	1			T38	168		T20	24		T22	1177
all_values[30]	auto[1]	auto[0]	auto[1]	33678	1			T20	2		T23	13		T48	4
all_values[30]	auto[1]	auto[1]	auto[1]	33200	1			T23	13		T48	1		T112	19
all_values[31]	auto[0]	auto[0]	auto[0]	2564558	1			T33	204		T34	230		T35	242
all_values[31]	auto[0]	auto[0]	auto[1]	2171192	1			T38	159		T20	29		T22	749
all_values[31]	auto[0]	auto[1]	auto[0]	241601	1			T38	18		T20	25		T22	113
all_values[31]	auto[0]	auto[1]	auto[1]	2133282	1			T38	145		T20	8		T22	1322
all_values[31]	auto[1]	auto[0]	auto[1]	33833	1			T20	2		T23	19		T48	6
all_values[31]	auto[1]	auto[1]	auto[1]	32975	1			T20	1		T23	16		T48	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal