Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[1]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[2]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[3]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[4]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[5]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[6]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[7]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[8]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[9]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[10]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[11]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[12]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[13]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[14]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[15]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[16]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[17]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[18]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[19]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[20]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[21]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[22]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[23]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[24]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[25]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[26]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[27]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[28]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[29]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[30]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[31]	7121428	1			T33	284		T34	340		T35	480

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119237289

1

T33

5818

T34

3592

T35

12327

auto[1]

108648407

1

T33

3270

T34

7288

T35

3033

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

189157365

1

T33

6540

T34

7404

T35

11845

auto[1]

38728331

1

T33

2548

T34

3476

T35

3515

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177817115

1

T33

6494

T34

7365

T35

8031

auto[1]

50068581

1

T33

2594

T34

3515

T35

7329

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2558244	1			T33	91		T34	50		T35	143
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2388600	1			T33	68		T34	101		T35	17
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	605443	1			T33	50		T34	65		T35	46
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	562804	1			T33	40		T35	192		T36	37
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	401159	1			T34	52		T35	29		T36	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	605178	1			T33	35		T34	72		T35	53
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2566096	1			T33	109		T34	60		T35	186
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2385988	1			T33	58		T34	123		T35	17
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	612956	1			T33	49		T34	62		T35	74
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	559830	1			T33	32		T35	122		T36	63
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	395992	1			T34	44		T35	20		T36	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	600566	1			T33	36		T34	51		T35	61
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2549315	1			T33	110		T34	55		T35	157
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2399546	1			T33	60		T34	126		T35	24
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	607385	1			T33	34		T34	60		T35	59
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	559495	1			T33	34		T35	144		T36	96
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	399070	1			T34	51		T35	18		T36	10
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	606617	1			T33	46		T34	48		T35	78
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2558677	1			T33	104		T34	52		T35	156
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2387761	1			T33	59		T34	131		T35	12
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	606337	1			T33	30		T34	65		T35	102
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	565855	1			T33	44		T35	152		T36	76
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	401376	1			T34	48		T35	10		T36	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	601422	1			T33	47		T34	44		T35	48
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2550323	1			T33	97		T34	57		T35	185
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2393465	1			T33	67		T34	124		T35	13
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	609923	1			T33	36		T34	55		T35	37
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	563716	1			T33	40		T35	174		T36	67
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	400376	1			T34	42		T35	23		T36	12
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	603625	1			T33	44		T34	62		T35	48
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2558690	1			T33	142		T34	51		T35	177
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2391936	1			T33	53		T34	134		T35	21
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	606712	1			T33	25		T34	48		T35	49
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	559632	1			T33	44		T35	138		T36	38
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	400354	1			T34	75		T35	18		T36	4
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	604104	1			T33	20		T34	32		T35	77
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2557309	1			T33	104		T34	52		T35	197
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2391374	1			T33	63		T34	125		T35	22
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	609527	1			T33	41		T34	52		T35	35
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	561367	1			T33	44		T35	122		T36	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	398844	1			T34	47		T35	22		T36	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	603007	1			T33	32		T34	64		T35	82
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2556153	1			T33	92		T34	49		T35	165
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2393300	1			T33	62		T34	135		T35	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	609253	1			T33	62		T34	52		T35	76
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	561926	1			T33	22		T35	139		T36	33
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	395857	1			T34	48		T35	20		T37	114
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	604939	1			T33	46		T34	56		T35	51
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2553573	1			T33	108		T34	58		T35	215
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2392870	1			T33	63		T34	114		T35	16
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	609581	1			T33	22		T34	56		T35	27
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	561869	1			T33	33		T35	160		T36	37
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	399172	1			T34	72		T35	14		T36	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	604363	1			T33	58		T34	40		T35	48
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2561027	1			T33	113		T34	63		T35	156
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2391876	1			T33	56		T34	114		T35	20
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	602980	1			T33	63		T34	51		T35	47
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	563000	1			T33	22		T35	160		T36	68
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	397883	1			T34	50		T35	20		T36	10
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	604662	1			T33	30		T34	62		T35	77
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2565665	1			T33	117		T34	61		T35	209
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2384969	1			T33	48		T34	103		T35	25
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	610728	1			T33	35		T34	52		T35	38
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	560081	1			T33	42		T35	149		T36	55
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	398141	1			T34	52		T35	20		T36	6
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	601844	1			T33	42		T34	72		T35	39
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2551460	1			T33	103		T34	51		T35	206
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2394048	1			T33	66		T34	118		T35	28
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	608351	1			T33	32		T34	52		T35	87
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	561513	1			T33	51		T35	102		T36	23
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	400312	1			T34	58		T35	12		T36	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	605744	1			T33	32		T34	61		T35	45
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2568185	1			T33	96		T34	56		T35	204
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2379988	1			T33	60		T34	118		T35	31
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	608517	1			T33	32		T34	42		T35	57
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	560775	1			T33	32		T35	148		T36	21
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	401559	1			T34	66		T35	16		T36	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	602404	1			T33	64		T34	58		T35	24
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2571105	1			T33	116		T34	64		T35	117
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2377245	1			T33	53		T34	119		T35	23
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	607349	1			T33	44		T34	54		T35	73
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	561323	1			T33	39		T35	182		T36	92
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	401400	1			T34	65		T35	20		T36	7
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	603006	1			T33	32		T34	38		T35	65
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2554171	1			T33	93		T34	56		T35	155
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2391797	1			T33	62		T34	123		T35	19
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	611110	1			T33	41		T34	70		T35	53
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	562478	1			T33	40		T35	179		T36	65
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	400105	1			T34	37		T35	17		T36	14
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	601767	1			T33	48		T34	54		T35	57
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2557448	1			T33	109		T34	62		T35	123
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2392405	1			T33	60		T34	115		T35	19
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	609343	1			T33	52		T34	40		T35	70
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	560732	1			T33	35		T35	187		T36	58
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	399255	1			T34	55		T35	20		T36	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	602245	1			T33	28		T34	68		T35	61
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2551593	1			T33	97		T34	50		T35	114
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2402754	1			T33	62		T34	117		T35	5
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	605540	1			T33	41		T34	46		T35	34
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	561005	1			T33	44		T35	204		T36	47
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	399730	1			T34	77		T35	27		T36	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	600806	1			T33	40		T34	50		T35	96
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2560906	1			T33	100		T34	62		T35	190
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2389420	1			T33	66		T34	115		T35	14
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	605225	1			T33	34		T34	59		T35	54
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	563388	1			T33	46		T35	155		T36	70
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	401455	1			T34	50		T35	12		T36	21
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	601034	1			T33	38		T34	54		T35	55
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2555311	1			T33	96		T34	61		T35	181
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2393402	1			T33	67		T34	134		T35	21
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	606122	1			T33	46		T34	58		T35	46
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	564809	1			T33	41		T35	162		T36	32
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	401543	1			T34	52		T35	22		T36	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	600241	1			T33	34		T34	35		T35	48
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2559505	1			T33	94		T34	57		T35	212
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2389940	1			T33	66		T34	116		T35	22
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	611983	1			T33	36		T34	71		T35	22
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	560557	1			T33	36		T35	165		T36	23
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	398921	1			T34	50		T35	22		T36	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	600522	1			T33	52		T34	46		T35	37
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2554943	1			T33	87		T34	60		T35	216
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2394562	1			T33	66		T34	123		T35	26
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	608164	1			T33	44		T34	54		T35	53
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	560531	1			T33	39		T35	110		T36	77
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	399976	1			T34	61		T35	18		T36	11
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	603252	1			T33	48		T34	42		T35	57
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2560462	1			T33	106		T34	69		T35	152
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2390529	1			T33	64		T34	86		T35	23
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	608737	1			T33	26		T34	61		T35	51
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	561971	1			T33	42		T35	192		T36	61
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	401082	1			T34	52		T35	19		T36	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	598647	1			T33	46		T34	72		T35	43
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2552236	1			T33	109		T34	62		T35	249
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2396775	1			T33	58		T34	93		T35	26
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	606976	1			T33	18		T34	46		T35	62
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	560859	1			T33	64		T35	77		T36	28
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	400864	1			T34	52		T35	11		T36	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	603718	1			T33	35		T34	87		T35	55
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2550690	1			T33	100		T34	55		T35	112
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2396818	1			T33	57		T34	124		T35	13
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	607566	1			T33	51		T34	49		T35	36
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	563044	1			T33	26		T35	235		T36	49
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	401523	1			T34	44		T35	26		T36	6
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	601787	1			T33	50		T34	68		T35	58
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2555064	1			T33	101		T34	64		T35	196
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2400375	1			T33	66		T34	139		T35	25
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	606876	1			T33	33		T34	41		T35	52
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	560263	1			T33	40		T35	139		T36	59
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	399798	1			T34	40		T35	20		T36	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	599052	1			T33	44		T34	56		T35	48
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2552591	1			T33	88		T34	61		T35	222
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2390041	1			T33	63		T34	120		T35	20
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	611131	1			T33	46		T34	60		T35	72
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	561378	1			T33	36		T35	116		T36	38
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	404209	1			T34	59		T35	12		T37	82
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	602078	1			T33	51		T34	40		T35	38
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2544710	1			T33	118		T34	55		T35	171
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2406078	1			T33	57		T34	100		T35	33
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	609397	1			T33	34		T34	66		T35	84
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	559327	1			T33	48		T35	145		T36	45
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	400374	1			T34	64		T35	11		T36	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	601542	1			T33	27		T34	55		T35	36
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2550134	1			T33	110		T34	65		T35	177
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2399835	1			T33	53		T34	111		T35	18
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	606905	1			T33	42		T34	32		T35	67
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	564951	1			T33	29		T35	136		T36	51
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	399423	1			T34	56		T35	18		T36	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	600180	1			T33	50		T34	76		T35	64
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2548065	1			T33	90		T34	56		T35	151
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2399928	1			T33	67		T34	115		T35	14
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	602994	1			T33	40		T34	50		T35	41
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	563672	1			T33	55		T35	171		T36	53
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	402280	1			T34	72		T35	34		T36	14
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	604489	1			T33	32		T34	47		T35	69
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2558941	1			T33	112		T34	57		T35	190
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2390245	1			T33	51		T34	116		T35	18
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	604961	1			T33	25		T34	48		T35	38
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	562141	1			T33	44		T35	148		T36	40
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	400132	1			T34	67		T35	24		T36	4
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	605008	1			T33	52		T34	52		T35	62
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2555124	1			T33	99		T34	61		T35	180
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2395008	1			T33	68		T34	126		T35	15
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	606402	1			T33	34		T34	62		T35	94
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	563391	1			T33	53		T35	114		T36	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	402243	1			T34	69		T35	31		T36	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	599260	1			T33	30		T34	22		T35	46
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2555296	1			T33	91		T34	60		T35	170
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2390454	1			T33	68		T34	115		T35	15
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	606297	1			T33	37		T34	61		T35	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	565823	1			T33	44		T35	221		T36	64
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	403107	1			T34	52		T35	21		T36	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	600451	1			T33	44		T34	52		T35	36

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal