Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[1]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[2]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[3]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[4]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[5]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[6]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[7]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[8]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[9]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[10]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[11]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[12]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[13]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[14]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[15]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[16]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[17]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[18]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[19]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[20]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[21]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[22]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[23]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[24]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[25]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[26]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[27]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[28]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[29]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[30]	7121428	1			T33	284		T34	340		T35	480
bins_for_gpio_bits[31]	7121428	1			T33	284		T34	340		T35	480

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119237289

1

T33

5818

T34

3592

T35

12327

auto[1]

108648407

1

T33

3270

T34

7288

T35

3033

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119229244

1

T33

5813

T34

3602

T35

12320

auto[1]

108656452

1

T33

3275

T34

7278

T35

3040

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3617257	1			T33	172		T34	103		T35	370
bins_for_gpio_bits[0]	auto[0]	auto[1]	108973	1			T33	8		T34	13		T35	11
bins_for_gpio_bits[0]	auto[1]	auto[0]	109234	1			T33	9		T34	12		T35	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	3285964	1			T33	95		T34	212		T35	88
bins_for_gpio_bits[1]	auto[0]	auto[0]	3629729	1			T33	181		T34	106		T35	370
bins_for_gpio_bits[1]	auto[0]	auto[1]	108905	1			T33	9		T34	16		T35	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	109153	1			T33	9		T34	16		T35	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	3273641	1			T33	85		T34	202		T35	86
bins_for_gpio_bits[2]	auto[0]	auto[0]	3606979	1			T33	166		T34	99		T35	346
bins_for_gpio_bits[2]	auto[0]	auto[1]	108981	1			T33	12		T34	16		T35	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	109216	1			T33	12		T34	16		T35	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	3296252	1			T33	94		T34	209		T35	106
bins_for_gpio_bits[3]	auto[0]	auto[0]	3621953	1			T33	167		T34	105		T35	400
bins_for_gpio_bits[3]	auto[0]	auto[1]	108659	1			T33	10		T34	13		T35	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	108916	1			T33	11		T34	12		T35	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	3281900	1			T33	96		T34	210		T35	60
bins_for_gpio_bits[4]	auto[0]	auto[0]	3614758	1			T33	160		T34	96		T35	386
bins_for_gpio_bits[4]	auto[0]	auto[1]	108938	1			T33	13		T34	17		T35	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	109204	1			T33	13		T34	16		T35	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	3288528	1			T33	98		T34	211		T35	74
bins_for_gpio_bits[5]	auto[0]	auto[0]	3615959	1			T33	204		T34	89		T35	349
bins_for_gpio_bits[5]	auto[0]	auto[1]	108849	1			T33	7		T34	10		T35	14
bins_for_gpio_bits[5]	auto[1]	auto[0]	109075	1			T33	7		T34	10		T35	15
bins_for_gpio_bits[5]	auto[1]	auto[1]	3287545	1			T33	66		T34	231		T35	102
bins_for_gpio_bits[6]	auto[0]	auto[0]	3619032	1			T33	181		T34	91		T35	344
bins_for_gpio_bits[6]	auto[0]	auto[1]	108917	1			T33	8		T34	13		T35	10
bins_for_gpio_bits[6]	auto[1]	auto[0]	109171	1			T33	8		T34	13		T35	10
bins_for_gpio_bits[6]	auto[1]	auto[1]	3284308	1			T33	87		T34	223		T35	116
bins_for_gpio_bits[7]	auto[0]	auto[0]	3618080	1			T33	165		T34	88		T35	371
bins_for_gpio_bits[7]	auto[0]	auto[1]	109002	1			T33	11		T34	13		T35	9
bins_for_gpio_bits[7]	auto[1]	auto[0]	109252	1			T33	11		T34	13		T35	9
bins_for_gpio_bits[7]	auto[1]	auto[1]	3285094	1			T33	97		T34	226		T35	91
bins_for_gpio_bits[8]	auto[0]	auto[0]	3615957	1			T33	155		T34	103		T35	394
bins_for_gpio_bits[8]	auto[0]	auto[1]	108809	1			T33	8		T34	11		T35	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	109066	1			T33	8		T34	11		T35	8
bins_for_gpio_bits[8]	auto[1]	auto[1]	3287596	1			T33	113		T34	215		T35	70
bins_for_gpio_bits[9]	auto[0]	auto[0]	3618033	1			T33	189		T34	101		T35	354
bins_for_gpio_bits[9]	auto[0]	auto[1]	108669	1			T33	9		T34	14		T35	9
bins_for_gpio_bits[9]	auto[1]	auto[0]	108974	1			T33	9		T34	13		T35	9
bins_for_gpio_bits[9]	auto[1]	auto[1]	3285752	1			T33	77		T34	212		T35	108
bins_for_gpio_bits[10]	auto[0]	auto[0]	3627594	1			T33	183		T34	102		T35	389
bins_for_gpio_bits[10]	auto[0]	auto[1]	108594	1			T33	11		T34	11		T35	7
bins_for_gpio_bits[10]	auto[1]	auto[0]	108880	1			T33	11		T34	11		T35	7
bins_for_gpio_bits[10]	auto[1]	auto[1]	3276360	1			T33	79		T34	216		T35	77
bins_for_gpio_bits[11]	auto[0]	auto[0]	3612175	1			T33	177		T34	86		T35	386
bins_for_gpio_bits[11]	auto[0]	auto[1]	108882	1			T33	9		T34	17		T35	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	109149	1			T33	9		T34	17		T35	9
bins_for_gpio_bits[11]	auto[1]	auto[1]	3291222	1			T33	89		T34	220		T35	76
bins_for_gpio_bits[12]	auto[0]	auto[0]	3628328	1			T33	149		T34	88		T35	404
bins_for_gpio_bits[12]	auto[0]	auto[1]	108891	1			T33	11		T34	10		T35	5
bins_for_gpio_bits[12]	auto[1]	auto[0]	109149	1			T33	11		T34	10		T35	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	3275060	1			T33	113		T34	232		T35	66
bins_for_gpio_bits[13]	auto[0]	auto[0]	3631131	1			T33	190		T34	104		T35	358
bins_for_gpio_bits[13]	auto[0]	auto[1]	108413	1			T33	9		T34	14		T35	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	108646	1			T33	9		T34	14		T35	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	3273238	1			T33	76		T34	208		T35	94
bins_for_gpio_bits[14]	auto[0]	auto[0]	3618361	1			T33	163		T34	111		T35	377
bins_for_gpio_bits[14]	auto[0]	auto[1]	109157	1			T33	11		T34	15		T35	10
bins_for_gpio_bits[14]	auto[1]	auto[0]	109398	1			T33	11		T34	15		T35	10
bins_for_gpio_bits[14]	auto[1]	auto[1]	3284512	1			T33	99		T34	199		T35	83
bins_for_gpio_bits[15]	auto[0]	auto[0]	3618717	1			T33	187		T34	89		T35	367
bins_for_gpio_bits[15]	auto[0]	auto[1]	108542	1			T33	9		T34	13		T35	12
bins_for_gpio_bits[15]	auto[1]	auto[0]	108806	1			T33	9		T34	13		T35	13
bins_for_gpio_bits[15]	auto[1]	auto[1]	3285363	1			T33	79		T34	225		T35	88
bins_for_gpio_bits[16]	auto[0]	auto[0]	3609036	1			T33	172		T34	82		T35	340
bins_for_gpio_bits[16]	auto[0]	auto[1]	108891	1			T33	10		T34	14		T35	12
bins_for_gpio_bits[16]	auto[1]	auto[0]	109102	1			T33	10		T34	14		T35	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	3294399	1			T33	92		T34	230		T35	116
bins_for_gpio_bits[17]	auto[0]	auto[0]	3620815	1			T33	172		T34	108		T35	388
bins_for_gpio_bits[17]	auto[0]	auto[1]	108450	1			T33	8		T34	14		T35	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	108704	1			T33	8		T34	13		T35	11
bins_for_gpio_bits[17]	auto[1]	auto[1]	3283459	1			T33	96		T34	205		T35	70
bins_for_gpio_bits[18]	auto[0]	auto[0]	3617297	1			T33	173		T34	104		T35	378
bins_for_gpio_bits[18]	auto[0]	auto[1]	108654	1			T33	10		T34	15		T35	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	108945	1			T33	10		T34	15		T35	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	3286532	1			T33	91		T34	206		T35	80
bins_for_gpio_bits[19]	auto[0]	auto[0]	3622411	1			T33	154		T34	115		T35	393
bins_for_gpio_bits[19]	auto[0]	auto[1]	109382	1			T33	12		T34	14		T35	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	109634	1			T33	12		T34	13		T35	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	3280001	1			T33	106		T34	198		T35	75
bins_for_gpio_bits[20]	auto[0]	auto[0]	3614213	1			T33	158		T34	99		T35	369
bins_for_gpio_bits[20]	auto[0]	auto[1]	109137	1			T33	12		T34	15		T35	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	109425	1			T33	12		T34	15		T35	10
bins_for_gpio_bits[20]	auto[1]	auto[1]	3288653	1			T33	102		T34	211		T35	92
bins_for_gpio_bits[21]	auto[0]	auto[0]	3622354	1			T33	164		T34	114		T35	384
bins_for_gpio_bits[21]	auto[0]	auto[1]	108557	1			T33	10		T34	17		T35	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	108816	1			T33	10		T34	16		T35	11
bins_for_gpio_bits[21]	auto[1]	auto[1]	3281701	1			T33	100		T34	193		T35	74
bins_for_gpio_bits[22]	auto[0]	auto[0]	3610763	1			T33	181		T34	97		T35	377
bins_for_gpio_bits[22]	auto[0]	auto[1]	109050	1			T33	9		T34	11		T35	10
bins_for_gpio_bits[22]	auto[1]	auto[0]	109308	1			T33	10		T34	11		T35	11
bins_for_gpio_bits[22]	auto[1]	auto[1]	3292307	1			T33	84		T34	221		T35	82
bins_for_gpio_bits[23]	auto[0]	auto[0]	3612309	1			T33	165		T34	90		T35	373
bins_for_gpio_bits[23]	auto[0]	auto[1]	108744	1			T33	12		T34	15		T35	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	108991	1			T33	12		T34	14		T35	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	3291384	1			T33	95		T34	221		T35	87
bins_for_gpio_bits[24]	auto[0]	auto[0]	3613311	1			T33	164		T34	92		T35	381
bins_for_gpio_bits[24]	auto[0]	auto[1]	108652	1			T33	10		T34	14		T35	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	108892	1			T33	10		T34	13		T35	6
bins_for_gpio_bits[24]	auto[1]	auto[1]	3290573	1			T33	100		T34	221		T35	88
bins_for_gpio_bits[25]	auto[0]	auto[0]	3616282	1			T33	155		T34	109		T35	404
bins_for_gpio_bits[25]	auto[0]	auto[1]	108593	1			T33	14		T34	12		T35	6
bins_for_gpio_bits[25]	auto[1]	auto[0]	108818	1			T33	15		T34	12		T35	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	3287735	1			T33	100		T34	207		T35	64
bins_for_gpio_bits[26]	auto[0]	auto[0]	3603988	1			T33	190		T34	110		T35	391
bins_for_gpio_bits[26]	auto[0]	auto[1]	109229	1			T33	9		T34	11		T35	8
bins_for_gpio_bits[26]	auto[1]	auto[0]	109446	1			T33	10		T34	11		T35	9
bins_for_gpio_bits[26]	auto[1]	auto[1]	3298765	1			T33	75		T34	208		T35	72
bins_for_gpio_bits[27]	auto[0]	auto[0]	3612862	1			T33	170		T34	84		T35	370
bins_for_gpio_bits[27]	auto[0]	auto[1]	108871	1			T33	11		T34	13		T35	10
bins_for_gpio_bits[27]	auto[1]	auto[0]	109128	1			T33	11		T34	13		T35	10
bins_for_gpio_bits[27]	auto[1]	auto[1]	3290567	1			T33	92		T34	230		T35	90
bins_for_gpio_bits[28]	auto[0]	auto[0]	3605591	1			T33	174		T34	91		T35	353
bins_for_gpio_bits[28]	auto[0]	auto[1]	108892	1			T33	11		T34	15		T35	10
bins_for_gpio_bits[28]	auto[1]	auto[0]	109140	1			T33	11		T34	15		T35	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	3297805	1			T33	88		T34	219		T35	107
bins_for_gpio_bits[29]	auto[0]	auto[0]	3617124	1			T33	172		T34	93		T35	366
bins_for_gpio_bits[29]	auto[0]	auto[1]	108686	1			T33	9		T34	12		T35	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	108919	1			T33	9		T34	12		T35	10
bins_for_gpio_bits[29]	auto[1]	auto[1]	3286699	1			T33	94		T34	223		T35	94
bins_for_gpio_bits[30]	auto[0]	auto[0]	3616197	1			T33	177		T34	110		T35	381
bins_for_gpio_bits[30]	auto[0]	auto[1]	108492	1			T33	9		T34	13		T35	6
bins_for_gpio_bits[30]	auto[1]	auto[0]	108720	1			T33	9		T34	13		T35	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	3288019	1			T33	89		T34	204		T35	86
bins_for_gpio_bits[31]	auto[0]	auto[0]	3618226	1			T33	161		T34	104		T35	400
bins_for_gpio_bits[31]	auto[0]	auto[1]	108961	1			T33	11		T34	18		T35	8
bins_for_gpio_bits[31]	auto[1]	auto[0]	109190	1			T33	11		T34	17		T35	8
bins_for_gpio_bits[31]	auto[1]	auto[1]	3285051	1			T33	101		T34	201		T35	64