Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4747837 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2429604 |
1 |
|
|
T38 |
204 |
|
T20 |
52 |
|
T22 |
940 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6871220 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
306221 |
1 |
|
|
T38 |
10 |
|
T20 |
2 |
|
T22 |
263 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4760512 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2416929 |
1 |
|
|
T38 |
202 |
|
T20 |
27 |
|
T22 |
1366 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1057792 |
1 |
|
|
T38 |
84 |
|
T20 |
3 |
|
T22 |
726 |
| auto[1] |
auto[0] |
auto[1] |
153705 |
1 |
|
|
T38 |
5 |
|
T22 |
174 |
|
T23 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1052916 |
1 |
|
|
T38 |
108 |
|
T20 |
22 |
|
T22 |
377 |
| auto[1] |
auto[1] |
auto[1] |
152516 |
1 |
|
|
T38 |
5 |
|
T20 |
2 |
|
T22 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4758560 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2418881 |
1 |
|
|
T38 |
164 |
|
T20 |
38 |
|
T22 |
1286 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6872430 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
305011 |
1 |
|
|
T38 |
12 |
|
T20 |
1 |
|
T22 |
188 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4769870 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2407571 |
1 |
|
|
T38 |
202 |
|
T20 |
37 |
|
T22 |
1027 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1052280 |
1 |
|
|
T38 |
103 |
|
T20 |
25 |
|
T22 |
288 |
| auto[1] |
auto[0] |
auto[1] |
152759 |
1 |
|
|
T38 |
8 |
|
T22 |
71 |
|
T23 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1050280 |
1 |
|
|
T38 |
87 |
|
T20 |
11 |
|
T22 |
551 |
| auto[1] |
auto[1] |
auto[1] |
152252 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T22 |
117 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4761682 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2415759 |
1 |
|
|
T38 |
210 |
|
T20 |
40 |
|
T22 |
755 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6871877 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
305564 |
1 |
|
|
T38 |
13 |
|
T20 |
2 |
|
T22 |
233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4767809 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2409632 |
1 |
|
|
T38 |
232 |
|
T20 |
29 |
|
T22 |
1210 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1055386 |
1 |
|
|
T38 |
101 |
|
T20 |
19 |
|
T22 |
623 |
| auto[1] |
auto[0] |
auto[1] |
152968 |
1 |
|
|
T38 |
5 |
|
T20 |
1 |
|
T22 |
140 |
| auto[1] |
auto[1] |
auto[0] |
1048682 |
1 |
|
|
T38 |
118 |
|
T20 |
8 |
|
T22 |
354 |
| auto[1] |
auto[1] |
auto[1] |
152596 |
1 |
|
|
T38 |
8 |
|
T20 |
1 |
|
T22 |
93 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4757525 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2419916 |
1 |
|
|
T38 |
168 |
|
T20 |
39 |
|
T22 |
1067 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6868840 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
308601 |
1 |
|
|
T38 |
10 |
|
T20 |
1 |
|
T22 |
173 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4755571 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2421870 |
1 |
|
|
T38 |
180 |
|
T20 |
16 |
|
T22 |
896 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1059928 |
1 |
|
|
T38 |
91 |
|
T20 |
3 |
|
T22 |
441 |
| auto[1] |
auto[0] |
auto[1] |
154513 |
1 |
|
|
T38 |
5 |
|
T22 |
104 |
|
T23 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1053341 |
1 |
|
|
T38 |
79 |
|
T20 |
12 |
|
T22 |
282 |
| auto[1] |
auto[1] |
auto[1] |
154088 |
1 |
|
|
T38 |
5 |
|
T20 |
1 |
|
T22 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4737886 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2439555 |
1 |
|
|
T38 |
183 |
|
T20 |
30 |
|
T22 |
1272 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6867615 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
309826 |
1 |
|
|
T38 |
6 |
|
T20 |
2 |
|
T22 |
183 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4739866 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2437575 |
1 |
|
|
T38 |
154 |
|
T20 |
42 |
|
T22 |
941 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1065774 |
1 |
|
|
T38 |
76 |
|
T20 |
24 |
|
T22 |
310 |
| auto[1] |
auto[0] |
auto[1] |
155454 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T22 |
72 |
| auto[1] |
auto[1] |
auto[0] |
1061975 |
1 |
|
|
T38 |
72 |
|
T20 |
16 |
|
T22 |
448 |
| auto[1] |
auto[1] |
auto[1] |
154372 |
1 |
|
|
T38 |
2 |
|
T20 |
1 |
|
T22 |
111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4754353 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2423088 |
1 |
|
|
T38 |
131 |
|
T20 |
34 |
|
T22 |
984 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870195 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
307246 |
1 |
|
|
T38 |
8 |
|
T20 |
2 |
|
T22 |
213 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4757615 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2419826 |
1 |
|
|
T38 |
182 |
|
T20 |
38 |
|
T22 |
1019 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1061573 |
1 |
|
|
T38 |
116 |
|
T20 |
29 |
|
T22 |
390 |
| auto[1] |
auto[0] |
auto[1] |
153889 |
1 |
|
|
T38 |
6 |
|
T20 |
2 |
|
T22 |
110 |
| auto[1] |
auto[1] |
auto[0] |
1051007 |
1 |
|
|
T38 |
58 |
|
T20 |
7 |
|
T22 |
416 |
| auto[1] |
auto[1] |
auto[1] |
153357 |
1 |
|
|
T38 |
2 |
|
T22 |
103 |
|
T23 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4746250 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2431191 |
1 |
|
|
T38 |
185 |
|
T20 |
46 |
|
T22 |
1230 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870859 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
306582 |
1 |
|
|
T38 |
12 |
|
T20 |
1 |
|
T22 |
202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4764805 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2412636 |
1 |
|
|
T38 |
161 |
|
T20 |
28 |
|
T22 |
1147 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1051773 |
1 |
|
|
T38 |
97 |
|
T20 |
8 |
|
T22 |
453 |
| auto[1] |
auto[0] |
auto[1] |
153058 |
1 |
|
|
T38 |
8 |
|
T20 |
1 |
|
T22 |
104 |
| auto[1] |
auto[1] |
auto[0] |
1054281 |
1 |
|
|
T38 |
52 |
|
T20 |
19 |
|
T22 |
492 |
| auto[1] |
auto[1] |
auto[1] |
153524 |
1 |
|
|
T38 |
4 |
|
T22 |
98 |
|
T23 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4742908 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2434533 |
1 |
|
|
T38 |
191 |
|
T20 |
19 |
|
T22 |
1387 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870681 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
306760 |
1 |
|
|
T38 |
12 |
|
T22 |
206 |
|
T23 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4765726 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2411715 |
1 |
|
|
T38 |
193 |
|
T20 |
32 |
|
T22 |
1050 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1059500 |
1 |
|
|
T38 |
93 |
|
T20 |
17 |
|
T22 |
284 |
| auto[1] |
auto[0] |
auto[1] |
154078 |
1 |
|
|
T38 |
6 |
|
T22 |
70 |
|
T23 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1045455 |
1 |
|
|
T38 |
88 |
|
T20 |
15 |
|
T22 |
560 |
| auto[1] |
auto[1] |
auto[1] |
152682 |
1 |
|
|
T38 |
6 |
|
T22 |
136 |
|
T23 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4779934 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2397507 |
1 |
|
|
T38 |
188 |
|
T20 |
36 |
|
T22 |
1318 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6871747 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
305694 |
1 |
|
|
T38 |
12 |
|
T22 |
225 |
|
T23 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4771086 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2406355 |
1 |
|
|
T38 |
192 |
|
T20 |
21 |
|
T22 |
1145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1061746 |
1 |
|
|
T38 |
101 |
|
T20 |
20 |
|
T22 |
275 |
| auto[1] |
auto[0] |
auto[1] |
154581 |
1 |
|
|
T38 |
8 |
|
T22 |
71 |
|
T23 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1038915 |
1 |
|
|
T38 |
79 |
|
T20 |
1 |
|
T22 |
645 |
| auto[1] |
auto[1] |
auto[1] |
151113 |
1 |
|
|
T38 |
4 |
|
T22 |
154 |
|
T23 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4770374 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2407067 |
1 |
|
|
T38 |
192 |
|
T20 |
38 |
|
T22 |
1165 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870160 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
307281 |
1 |
|
|
T38 |
14 |
|
T20 |
1 |
|
T22 |
233 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4751783 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2425658 |
1 |
|
|
T38 |
221 |
|
T20 |
40 |
|
T22 |
1188 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1069896 |
1 |
|
|
T38 |
103 |
|
T20 |
28 |
|
T22 |
440 |
| auto[1] |
auto[0] |
auto[1] |
155704 |
1 |
|
|
T38 |
8 |
|
T20 |
1 |
|
T22 |
106 |
| auto[1] |
auto[1] |
auto[0] |
1048481 |
1 |
|
|
T38 |
104 |
|
T20 |
11 |
|
T22 |
515 |
| auto[1] |
auto[1] |
auto[1] |
151577 |
1 |
|
|
T38 |
6 |
|
T22 |
127 |
|
T23 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4762710 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2414731 |
1 |
|
|
T38 |
135 |
|
T20 |
28 |
|
T22 |
640 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6867419 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
310022 |
1 |
|
|
T38 |
14 |
|
T20 |
1 |
|
T22 |
227 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4743105 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2434336 |
1 |
|
|
T38 |
225 |
|
T20 |
23 |
|
T22 |
1161 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1070987 |
1 |
|
|
T38 |
140 |
|
T20 |
12 |
|
T22 |
592 |
| auto[1] |
auto[0] |
auto[1] |
156138 |
1 |
|
|
T38 |
7 |
|
T20 |
1 |
|
T22 |
151 |
| auto[1] |
auto[1] |
auto[0] |
1053327 |
1 |
|
|
T38 |
71 |
|
T20 |
10 |
|
T22 |
342 |
| auto[1] |
auto[1] |
auto[1] |
153884 |
1 |
|
|
T38 |
7 |
|
T22 |
76 |
|
T23 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4750599 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2426842 |
1 |
|
|
T38 |
147 |
|
T20 |
31 |
|
T22 |
645 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6867679 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
309762 |
1 |
|
|
T38 |
8 |
|
T20 |
1 |
|
T22 |
236 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4743247 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2434194 |
1 |
|
|
T38 |
189 |
|
T20 |
43 |
|
T22 |
1183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1067500 |
1 |
|
|
T38 |
113 |
|
T20 |
25 |
|
T22 |
645 |
| auto[1] |
auto[0] |
auto[1] |
154866 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T22 |
163 |
| auto[1] |
auto[1] |
auto[0] |
1056932 |
1 |
|
|
T38 |
68 |
|
T20 |
17 |
|
T22 |
302 |
| auto[1] |
auto[1] |
auto[1] |
154896 |
1 |
|
|
T38 |
2 |
|
T22 |
73 |
|
T23 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4761383 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2416058 |
1 |
|
|
T38 |
179 |
|
T20 |
24 |
|
T22 |
1168 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6868759 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
308682 |
1 |
|
|
T38 |
5 |
|
T22 |
249 |
|
T23 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4755947 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2421494 |
1 |
|
|
T38 |
139 |
|
T20 |
36 |
|
T22 |
1276 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1070297 |
1 |
|
|
T38 |
69 |
|
T20 |
28 |
|
T22 |
517 |
| auto[1] |
auto[0] |
auto[1] |
156559 |
1 |
|
|
T38 |
3 |
|
T22 |
130 |
|
T64 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1042515 |
1 |
|
|
T38 |
65 |
|
T20 |
8 |
|
T22 |
510 |
| auto[1] |
auto[1] |
auto[1] |
152123 |
1 |
|
|
T38 |
2 |
|
T22 |
119 |
|
T23 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4766780 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2410661 |
1 |
|
|
T38 |
224 |
|
T20 |
44 |
|
T22 |
1114 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6871470 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
305971 |
1 |
|
|
T38 |
10 |
|
T20 |
1 |
|
T22 |
204 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4768871 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2408570 |
1 |
|
|
T38 |
198 |
|
T20 |
22 |
|
T22 |
1014 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1058546 |
1 |
|
|
T38 |
84 |
|
T20 |
11 |
|
T22 |
423 |
| auto[1] |
auto[0] |
auto[1] |
153932 |
1 |
|
|
T38 |
5 |
|
T20 |
1 |
|
T22 |
110 |
| auto[1] |
auto[1] |
auto[0] |
1044053 |
1 |
|
|
T38 |
104 |
|
T20 |
10 |
|
T22 |
387 |
| auto[1] |
auto[1] |
auto[1] |
152039 |
1 |
|
|
T38 |
5 |
|
T22 |
94 |
|
T23 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4753349 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2424092 |
1 |
|
|
T38 |
147 |
|
T20 |
43 |
|
T22 |
1152 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6871957 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
305484 |
1 |
|
|
T38 |
11 |
|
T20 |
2 |
|
T22 |
235 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4771861 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2405580 |
1 |
|
|
T38 |
214 |
|
T20 |
35 |
|
T22 |
1192 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1057124 |
1 |
|
|
T38 |
104 |
|
T20 |
22 |
|
T22 |
392 |
| auto[1] |
auto[0] |
auto[1] |
154346 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T22 |
102 |
| auto[1] |
auto[1] |
auto[0] |
1042972 |
1 |
|
|
T38 |
99 |
|
T20 |
11 |
|
T22 |
565 |
| auto[1] |
auto[1] |
auto[1] |
151138 |
1 |
|
|
T38 |
5 |
|
T20 |
1 |
|
T22 |
133 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4763562 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2413879 |
1 |
|
|
T38 |
138 |
|
T20 |
29 |
|
T22 |
1048 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870433 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
307008 |
1 |
|
|
T38 |
12 |
|
T20 |
1 |
|
T22 |
200 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4763481 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2413960 |
1 |
|
|
T38 |
228 |
|
T20 |
20 |
|
T22 |
983 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1059780 |
1 |
|
|
T38 |
129 |
|
T20 |
19 |
|
T22 |
399 |
| auto[1] |
auto[0] |
auto[1] |
154237 |
1 |
|
|
T38 |
7 |
|
T20 |
1 |
|
T22 |
106 |
| auto[1] |
auto[1] |
auto[0] |
1047172 |
1 |
|
|
T38 |
87 |
|
T22 |
384 |
|
T23 |
297 |
| auto[1] |
auto[1] |
auto[1] |
152771 |
1 |
|
|
T38 |
5 |
|
T22 |
94 |
|
T23 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4753026 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2424415 |
1 |
|
|
T38 |
179 |
|
T20 |
48 |
|
T22 |
1018 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870460 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
306981 |
1 |
|
|
T38 |
12 |
|
T20 |
1 |
|
T22 |
255 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4761858 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2415583 |
1 |
|
|
T38 |
285 |
|
T20 |
53 |
|
T22 |
1334 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1055585 |
1 |
|
|
T38 |
146 |
|
T20 |
20 |
|
T22 |
576 |
| auto[1] |
auto[0] |
auto[1] |
153251 |
1 |
|
|
T38 |
5 |
|
T20 |
1 |
|
T22 |
138 |
| auto[1] |
auto[1] |
auto[0] |
1053017 |
1 |
|
|
T38 |
127 |
|
T20 |
32 |
|
T22 |
503 |
| auto[1] |
auto[1] |
auto[1] |
153730 |
1 |
|
|
T38 |
7 |
|
T22 |
117 |
|
T23 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |