Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4743042 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2434399 |
1 |
|
|
T38 |
172 |
|
T20 |
36 |
|
T22 |
1072 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6870323 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
307118 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T22 |
212 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4761636 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2415805 |
1 |
|
|
T38 |
116 |
|
T20 |
23 |
|
T22 |
1112 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1051842 |
1 |
|
|
T38 |
74 |
|
T20 |
17 |
|
T22 |
457 |
| auto[1] |
auto[0] |
auto[1] |
152188 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T22 |
112 |
| auto[1] |
auto[1] |
auto[0] |
1056845 |
1 |
|
|
T38 |
36 |
|
T20 |
5 |
|
T22 |
443 |
| auto[1] |
auto[1] |
auto[1] |
154930 |
1 |
|
|
T22 |
100 |
|
T23 |
11 |
|
T64 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |