Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4765825 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2411616 |
1 |
|
|
T38 |
169 |
|
T20 |
37 |
|
T22 |
856 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6871875 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
305566 |
1 |
|
|
T38 |
10 |
|
T20 |
2 |
|
T22 |
141 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4769720 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2407721 |
1 |
|
|
T38 |
163 |
|
T20 |
21 |
|
T22 |
790 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1068078 |
1 |
|
|
T38 |
108 |
|
T20 |
9 |
|
T22 |
368 |
| auto[1] |
auto[0] |
auto[1] |
155538 |
1 |
|
|
T38 |
6 |
|
T20 |
1 |
|
T22 |
85 |
| auto[1] |
auto[1] |
auto[0] |
1034077 |
1 |
|
|
T38 |
45 |
|
T20 |
10 |
|
T22 |
281 |
| auto[1] |
auto[1] |
auto[1] |
150028 |
1 |
|
|
T38 |
4 |
|
T20 |
1 |
|
T22 |
56 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |