Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4770762 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2406679 |
1 |
|
|
T38 |
223 |
|
T20 |
31 |
|
T22 |
889 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6868755 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
308686 |
1 |
|
|
T38 |
9 |
|
T20 |
1 |
|
T22 |
225 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4745563 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2431878 |
1 |
|
|
T38 |
155 |
|
T20 |
21 |
|
T22 |
1143 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1073172 |
1 |
|
|
T38 |
57 |
|
T20 |
12 |
|
T22 |
553 |
| auto[1] |
auto[0] |
auto[1] |
157149 |
1 |
|
|
T38 |
3 |
|
T20 |
1 |
|
T22 |
129 |
| auto[1] |
auto[1] |
auto[0] |
1050020 |
1 |
|
|
T38 |
89 |
|
T20 |
8 |
|
T22 |
365 |
| auto[1] |
auto[1] |
auto[1] |
151537 |
1 |
|
|
T38 |
6 |
|
T22 |
96 |
|
T23 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |