Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4759763 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2417678 |
1 |
|
|
T38 |
167 |
|
T20 |
32 |
|
T22 |
1030 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6871722 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
305719 |
1 |
|
|
T38 |
9 |
|
T20 |
3 |
|
T22 |
238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4767508 |
1 |
|
|
T33 |
204 |
|
T34 |
230 |
|
T35 |
242 |
| auto[1] |
2409933 |
1 |
|
|
T38 |
215 |
|
T20 |
38 |
|
T22 |
1252 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1048499 |
1 |
|
|
T38 |
128 |
|
T20 |
34 |
|
T22 |
529 |
| auto[1] |
auto[0] |
auto[1] |
152796 |
1 |
|
|
T38 |
4 |
|
T20 |
3 |
|
T22 |
121 |
| auto[1] |
auto[1] |
auto[0] |
1055715 |
1 |
|
|
T38 |
78 |
|
T20 |
1 |
|
T22 |
485 |
| auto[1] |
auto[1] |
auto[1] |
152923 |
1 |
|
|
T38 |
5 |
|
T22 |
117 |
|
T23 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |