Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1480775	1			T23	1		T24	1		T25	1
all_pins[1]	1480775	1			T23	1		T24	1		T25	1
all_pins[2]	1480775	1			T23	1		T24	1		T25	1
all_pins[3]	1480775	1			T23	1		T24	1		T25	1
all_pins[4]	1480775	1			T23	1		T24	1		T25	1
all_pins[5]	1480775	1			T23	1		T24	1		T25	1
all_pins[6]	1480775	1			T23	1		T24	1		T25	1
all_pins[7]	1480775	1			T23	1		T24	1		T25	1
all_pins[8]	1480775	1			T23	1		T24	1		T25	1
all_pins[9]	1480775	1			T23	1		T24	1		T25	1
all_pins[10]	1480775	1			T23	1		T24	1		T25	1
all_pins[11]	1480775	1			T23	1		T24	1		T25	1
all_pins[12]	1480775	1			T23	1		T24	1		T25	1
all_pins[13]	1480775	1			T23	1		T24	1		T25	1
all_pins[14]	1480775	1			T23	1		T24	1		T25	1
all_pins[15]	1480775	1			T23	1		T24	1		T25	1
all_pins[16]	1480775	1			T23	1		T24	1		T25	1
all_pins[17]	1480775	1			T23	1		T24	1		T25	1
all_pins[18]	1480775	1			T23	1		T24	1		T25	1
all_pins[19]	1480775	1			T23	1		T24	1		T25	1
all_pins[20]	1480775	1			T23	1		T24	1		T25	1
all_pins[21]	1480775	1			T23	1		T24	1		T25	1
all_pins[22]	1480775	1			T23	1		T24	1		T25	1
all_pins[23]	1480775	1			T23	1		T24	1		T25	1
all_pins[24]	1480775	1			T23	1		T24	1		T25	1
all_pins[25]	1480775	1			T23	1		T24	1		T25	1
all_pins[26]	1480775	1			T23	1		T24	1		T25	1
all_pins[27]	1480775	1			T23	1		T24	1		T25	1
all_pins[28]	1480775	1			T23	1		T24	1		T25	1
all_pins[29]	1480775	1			T23	1		T24	1		T25	1
all_pins[30]	1480775	1			T23	1		T24	1		T25	1
all_pins[31]	1480775	1			T23	1		T24	1		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	29432567	1			T23	32		T24	32		T25	32
values[0x1]	17952233	1			T28	1691		T29	12162		T31	457
transitions[0x0=>0x1]	10734689	1			T28	1019		T29	7007		T31	305
transitions[0x1=>0x0]	10734537	1			T28	1019		T29	7006		T31	305

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	919309	1			T23	1		T24	1		T25	1
all_pins[0]	values[0x1]	561466	1			T28	52		T29	303		T31	31
all_pins[0]	transitions[0x0=>0x1]	347977	1			T28	24		T29	202		T31	25
all_pins[0]	transitions[0x1=>0x0]	344651	1			T28	24		T29	270		T31	7
all_pins[1]	values[0x0]	918978	1			T23	1		T24	1		T25	1
all_pins[1]	values[0x1]	561797	1			T28	54		T29	336		T31	9
all_pins[1]	transitions[0x0=>0x1]	335654	1			T28	32		T29	234		T31	4
all_pins[1]	transitions[0x1=>0x0]	335323	1			T28	30		T29	201		T31	26
all_pins[2]	values[0x0]	921463	1			T23	1		T24	1		T25	1
all_pins[2]	values[0x1]	559312	1			T28	43		T29	344		T31	15
all_pins[2]	transitions[0x0=>0x1]	333854	1			T28	30		T29	192		T31	11
all_pins[2]	transitions[0x1=>0x0]	336339	1			T28	41		T29	184		T31	5
all_pins[3]	values[0x0]	920067	1			T23	1		T24	1		T25	1
all_pins[3]	values[0x1]	560708	1			T28	78		T29	347		T31	5
all_pins[3]	transitions[0x0=>0x1]	335753	1			T28	46		T29	221		T31	5
all_pins[3]	transitions[0x1=>0x0]	334357	1			T28	11		T29	218		T31	15
all_pins[4]	values[0x0]	920779	1			T23	1		T24	1		T25	1
all_pins[4]	values[0x1]	559996	1			T28	57		T29	370		T31	16
all_pins[4]	transitions[0x0=>0x1]	335379	1			T28	21		T29	222		T31	13
all_pins[4]	transitions[0x1=>0x0]	336091	1			T28	42		T29	199		T31	2
all_pins[5]	values[0x0]	917449	1			T23	1		T24	1		T25	1
all_pins[5]	values[0x1]	563326	1			T28	48		T29	413		T31	16
all_pins[5]	transitions[0x0=>0x1]	337068	1			T28	24		T29	226		T31	9
all_pins[5]	transitions[0x1=>0x0]	333738	1			T28	33		T29	183		T31	9
all_pins[6]	values[0x0]	919582	1			T23	1		T24	1		T25	1
all_pins[6]	values[0x1]	561193	1			T28	75		T29	404		T31	11
all_pins[6]	transitions[0x0=>0x1]	333451	1			T28	54		T29	229		T31	6
all_pins[6]	transitions[0x1=>0x0]	335584	1			T28	27		T29	238		T31	11
all_pins[7]	values[0x0]	919875	1			T23	1		T24	1		T25	1
all_pins[7]	values[0x1]	560900	1			T28	55		T29	328		T31	13
all_pins[7]	transitions[0x0=>0x1]	335591	1			T28	36		T29	170		T31	13
all_pins[7]	transitions[0x1=>0x0]	335884	1			T28	56		T29	246		T31	11
all_pins[8]	values[0x0]	922401	1			T23	1		T24	1		T25	1
all_pins[8]	values[0x1]	558374	1			T28	48		T29	324		T31	15
all_pins[8]	transitions[0x0=>0x1]	333443	1			T28	28		T29	213		T31	8
all_pins[8]	transitions[0x1=>0x0]	335969	1			T28	35		T29	217		T31	6
all_pins[9]	values[0x0]	921752	1			T23	1		T24	1		T25	1
all_pins[9]	values[0x1]	559023	1			T28	36		T29	392		T31	7
all_pins[9]	transitions[0x0=>0x1]	333772	1			T28	33		T29	281		T31	7
all_pins[9]	transitions[0x1=>0x0]	333123	1			T28	45		T29	213		T31	15
all_pins[10]	values[0x0]	921564	1			T23	1		T24	1		T25	1
all_pins[10]	values[0x1]	559211	1			T28	76		T29	340		T31	30
all_pins[10]	transitions[0x0=>0x1]	335122	1			T28	55		T29	220		T31	30
all_pins[10]	transitions[0x1=>0x0]	334934	1			T28	15		T29	272		T31	7
all_pins[11]	values[0x0]	920905	1			T23	1		T24	1		T25	1
all_pins[11]	values[0x1]	559870	1			T28	58		T29	440		T31	3
all_pins[11]	transitions[0x0=>0x1]	335492	1			T28	31		T29	260		T32	19
all_pins[11]	transitions[0x1=>0x0]	334833	1			T28	49		T29	160		T31	27
all_pins[12]	values[0x0]	920572	1			T23	1		T24	1		T25	1
all_pins[12]	values[0x1]	560203	1			T28	58		T29	305		T31	16
all_pins[12]	transitions[0x0=>0x1]	335430	1			T28	28		T29	145		T31	16
all_pins[12]	transitions[0x1=>0x0]	335097	1			T28	28		T29	280		T31	3
all_pins[13]	values[0x0]	921405	1			T23	1		T24	1		T25	1
all_pins[13]	values[0x1]	559370	1			T28	52		T29	477		T31	8
all_pins[13]	transitions[0x0=>0x1]	333719	1			T28	26		T29	329		T31	1
all_pins[13]	transitions[0x1=>0x0]	334552	1			T28	32		T29	157		T31	9
all_pins[14]	values[0x0]	921251	1			T23	1		T24	1		T25	1
all_pins[14]	values[0x1]	559524	1			T28	51		T29	321		T31	6
all_pins[14]	transitions[0x0=>0x1]	335417	1			T28	38		T29	170		T31	3
all_pins[14]	transitions[0x1=>0x0]	335263	1			T28	39		T29	326		T31	5
all_pins[15]	values[0x0]	918648	1			T23	1		T24	1		T25	1
all_pins[15]	values[0x1]	562127	1			T28	50		T29	425		T31	8
all_pins[15]	transitions[0x0=>0x1]	336901	1			T28	36		T29	294		T31	6
all_pins[15]	transitions[0x1=>0x0]	334298	1			T28	37		T29	190		T31	4
all_pins[16]	values[0x0]	918941	1			T23	1		T24	1		T25	1
all_pins[16]	values[0x1]	561834	1			T28	46		T29	445		T31	20
all_pins[16]	transitions[0x0=>0x1]	334888	1			T28	23		T29	218		T31	19
all_pins[16]	transitions[0x1=>0x0]	335181	1			T28	27		T29	198		T31	7
all_pins[17]	values[0x0]	917337	1			T23	1		T24	1		T25	1
all_pins[17]	values[0x1]	563438	1			T28	46		T29	415		T31	23
all_pins[17]	transitions[0x0=>0x1]	336709	1			T28	18		T29	177		T31	9
all_pins[17]	transitions[0x1=>0x0]	335105	1			T28	18		T29	207		T31	6
all_pins[18]	values[0x0]	920394	1			T23	1		T24	1		T25	1
all_pins[18]	values[0x1]	560381	1			T28	31		T29	365		T31	2
all_pins[18]	transitions[0x0=>0x1]	334548	1			T28	17		T29	184		T31	1
all_pins[18]	transitions[0x1=>0x0]	337605	1			T28	32		T29	234		T31	22
all_pins[19]	values[0x0]	918777	1			T23	1		T24	1		T25	1
all_pins[19]	values[0x1]	561998	1			T28	48		T29	323		T31	8
all_pins[19]	transitions[0x0=>0x1]	335456	1			T28	37		T29	208		T31	6
all_pins[19]	transitions[0x1=>0x0]	333839	1			T28	20		T29	250		T32	15
all_pins[20]	values[0x0]	920740	1			T23	1		T24	1		T25	1
all_pins[20]	values[0x1]	560035	1			T28	64		T29	423		T31	9
all_pins[20]	transitions[0x0=>0x1]	332063	1			T28	30		T29	258		T31	7
all_pins[20]	transitions[0x1=>0x0]	334026	1			T28	14		T29	158		T31	6
all_pins[21]	values[0x0]	917488	1			T23	1		T24	1		T25	1
all_pins[21]	values[0x1]	563287	1			T28	30		T29	357		T31	30
all_pins[21]	transitions[0x0=>0x1]	336351	1			T28	16		T29	184		T31	23
all_pins[21]	transitions[0x1=>0x0]	333099	1			T28	50		T29	250		T31	2
all_pins[22]	values[0x0]	917202	1			T23	1		T24	1		T25	1
all_pins[22]	values[0x1]	563573	1			T28	52		T29	353		T31	16
all_pins[22]	transitions[0x0=>0x1]	336404	1			T28	42		T29	245		T31	1
all_pins[22]	transitions[0x1=>0x0]	336118	1			T28	20		T29	249		T31	15
all_pins[23]	values[0x0]	920696	1			T23	1		T24	1		T25	1
all_pins[23]	values[0x1]	560079	1			T28	55		T29	411		T31	15
all_pins[23]	transitions[0x0=>0x1]	332887	1			T28	38		T29	277		T31	9
all_pins[23]	transitions[0x1=>0x0]	336381	1			T28	35		T29	219		T31	10
all_pins[24]	values[0x0]	916277	1			T23	1		T24	1		T25	1
all_pins[24]	values[0x1]	564498	1			T28	61		T29	392		T31	18
all_pins[24]	transitions[0x0=>0x1]	337949	1			T28	34		T29	219		T31	12
all_pins[24]	transitions[0x1=>0x0]	333530	1			T28	28		T29	238		T31	9
all_pins[25]	values[0x0]	917035	1			T23	1		T24	1		T25	1
all_pins[25]	values[0x1]	563740	1			T28	49		T29	405		T31	16
all_pins[25]	transitions[0x0=>0x1]	335874	1			T28	27		T29	159		T31	8
all_pins[25]	transitions[0x1=>0x0]	336632	1			T28	39		T29	146		T31	10
all_pins[26]	values[0x0]	922655	1			T23	1		T24	1		T25	1
all_pins[26]	values[0x1]	558120	1			T28	61		T29	421		T31	9
all_pins[26]	transitions[0x0=>0x1]	332488	1			T28	33		T29	231		T31	4
all_pins[26]	transitions[0x1=>0x0]	338108	1			T28	21		T29	215		T31	11
all_pins[27]	values[0x0]	920561	1			T23	1		T24	1		T25	1
all_pins[27]	values[0x1]	560214	1			T28	49		T29	419		T31	15
all_pins[27]	transitions[0x0=>0x1]	336215	1			T28	29		T29	195		T31	11
all_pins[27]	transitions[0x1=>0x0]	334121	1			T28	41		T29	197		T31	5
all_pins[28]	values[0x0]	919711	1			T23	1		T24	1		T25	1
all_pins[28]	values[0x1]	561064	1			T28	55		T29	387		T31	24
all_pins[28]	transitions[0x0=>0x1]	334938	1			T28	39		T29	211		T31	15
all_pins[28]	transitions[0x1=>0x0]	334088	1			T28	33		T29	243		T31	6
all_pins[29]	values[0x0]	918755	1			T23	1		T24	1		T25	1
all_pins[29]	values[0x1]	562020	1			T28	41		T29	377		T31	11
all_pins[29]	transitions[0x0=>0x1]	335925	1			T28	25		T29	193		T31	2
all_pins[29]	transitions[0x1=>0x0]	334969	1			T28	39		T29	203		T31	15
all_pins[30]	values[0x0]	917515	1			T23	1		T24	1		T25	1
all_pins[30]	values[0x1]	563260	1			T28	60		T29	428		T31	19
all_pins[30]	transitions[0x0=>0x1]	335641	1			T28	43		T29	240		T31	9
all_pins[30]	transitions[0x1=>0x0]	334401	1			T28	24		T29	189		T31	1
all_pins[31]	values[0x0]	922483	1			T23	1		T24	1		T25	1
all_pins[31]	values[0x1]	558292	1			T28	52		T29	372		T31	13
all_pins[31]	transitions[0x0=>0x1]	332330	1			T28	26		T29	200		T31	12
all_pins[31]	transitions[0x1=>0x0]	337298	1			T28	34		T29	256		T31	18