Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[1]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[2]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[3]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[4]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[5]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[6]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[7]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[8]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[9]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[10]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[11]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[12]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[13]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[14]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[15]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[16]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[17]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[18]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[19]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[20]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[21]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[22]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[23]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[24]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[25]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[26]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[27]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[28]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[29]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[30]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[31]	6244868	1			T23	315		T24	773		T25	752

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101546082

1

T23

5984

T24

7148

T25

5344

auto[1]

98289694

1

T23

4096

T24

17588

T25

18720

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167755086

1

T23

8212

T24

14403

T25

17886

auto[1]

32080690

1

T23

1868

T24

10333

T25

6178

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158431242

1

T23

8252

T24

14440

T25

12367

auto[1]

41404534

1

T23

1828

T24

10296

T25

11697

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2250684	1			T23	122		T24	50		T25	25
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2197129	1			T23	104		T24	280		T25	177
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	508087	1			T23	21		T24	171		T25	125
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	421111	1			T23	32		T25	40		T26	16
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	370839	1			T24	154		T25	261		T26	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	497018	1			T23	36		T24	118		T25	124
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2243682	1			T23	114		T24	55		T25	40
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2205730	1			T23	102		T24	205		T25	233
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	507257	1			T23	36		T24	170		T25	143
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	417490	1			T23	27		T25	37		T26	80
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	370918	1			T24	161		T25	205		T26	14
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	499791	1			T23	36		T24	182		T25	94
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2238148	1			T23	108		T24	54		T25	48
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2204559	1			T23	116		T24	255		T25	220
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	504872	1			T23	12		T24	156		T25	93
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	423518	1			T23	55		T25	32		T26	65
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	372690	1			T24	172		T25	253		T26	9
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	501081	1			T23	24		T24	136		T25	106
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2238498	1			T23	122		T24	52		T25	16
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2206180	1			T23	104		T24	262		T25	126
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	503997	1			T23	18		T24	167		T25	64
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	421597	1			T23	36		T25	48		T26	98
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	374144	1			T24	142		T25	335		T26	21
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	500452	1			T23	35		T24	150		T25	163
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2241132	1			T23	133		T24	68		T25	35
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2204166	1			T23	93		T24	244		T25	240
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	502453	1			T23	26		T24	153		T25	109
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	424617	1			T23	32		T25	39		T26	98
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	373740	1			T24	156		T25	226		T26	19
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	498760	1			T23	31		T24	152		T25	103
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2239201	1			T23	134		T24	66		T25	37
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2206170	1			T23	104		T24	229		T25	248
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	504732	1			T23	26		T24	170		T25	158
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	422115	1			T23	25		T25	32		T26	80
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	374345	1			T24	166		T25	188		T26	15
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	498305	1			T23	26		T24	142		T25	89
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2247259	1			T23	113		T24	67		T25	47
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2198002	1			T23	105		T24	207		T25	319
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	506125	1			T23	14		T24	184		T25	82
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	421290	1			T23	45		T25	25		T26	93
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	373938	1			T24	162		T25	213		T26	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	498254	1			T23	38		T24	153		T25	66
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2249812	1			T23	140		T24	63		T25	36
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2192709	1			T23	96		T24	221		T25	286
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	507694	1			T23	40		T24	141		T25	62
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	422749	1			T23	19		T25	31		T26	74
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	371283	1			T24	176		T25	257		T26	9
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	500621	1			T23	20		T24	172		T25	80
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2246021	1			T23	120		T24	68		T25	32
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2200854	1			T23	102		T24	214		T25	271
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	505086	1			T23	38		T24	151		T25	93
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	421097	1			T23	32		T25	29		T26	88
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	373407	1			T24	170		T25	275		T26	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	498403	1			T23	23		T24	170		T25	52
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2253775	1			T23	145		T24	63		T25	41
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2196224	1			T23	93		T24	233		T25	281
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	506708	1			T23	30		T24	166		T25	100
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	421389	1			T23	28		T25	28		T26	94
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	369199	1			T24	156		T25	217		T26	16
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	497573	1			T23	19		T24	155		T25	85
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2245290	1			T23	125		T24	63		T25	38
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2202118	1			T23	105		T24	275		T25	288
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	502668	1			T23	22		T24	139		T25	84
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	421382	1			T23	45		T25	33		T26	61
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	373137	1			T24	162		T25	256		T26	9
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	500273	1			T23	18		T24	134		T25	53
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2243204	1			T23	150		T24	60		T25	34
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2200153	1			T23	90		T24	242		T25	237
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	503270	1			T23	36		T24	148		T25	95
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	423403	1			T23	23		T25	42		T26	100
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	374195	1			T24	175		T25	260		T26	13
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	500643	1			T23	16		T24	148		T25	84
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2241794	1			T23	133		T24	64		T25	39
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2206243	1			T23	101		T24	261		T25	251
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	505756	1			T23	21		T24	160		T25	106
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	419029	1			T23	28		T25	41		T26	72
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	370721	1			T24	144		T25	217		T26	15
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	501325	1			T23	32		T24	144		T25	98
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2258219	1			T23	122		T24	68		T25	42
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2190789	1			T23	101		T24	192		T25	232
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	507791	1			T23	44		T24	198		T25	128
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	420479	1			T23	16		T25	30		T26	86
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	370950	1			T24	129		T25	198		T26	18
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	496640	1			T23	32		T24	186		T25	122
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2256246	1			T23	123		T24	61		T25	27
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2191813	1			T23	101		T24	247		T25	204
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	501872	1			T23	44		T24	157		T25	82
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	422209	1			T23	14		T25	45		T26	88
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	373063	1			T24	144		T25	303		T26	12
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	499665	1			T23	33		T24	164		T25	91
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2245399	1			T23	130		T24	54		T25	45
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2200812	1			T23	86		T24	264		T25	275
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	505942	1			T23	12		T24	192		T25	150
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	422325	1			T23	51		T25	27		T26	102
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	371372	1			T24	126		T25	144		T26	17
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	499018	1			T23	36		T24	137		T25	111
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2254609	1			T23	140		T24	66		T25	32
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2195384	1			T23	100		T24	188		T25	292
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	500883	1			T23	28		T24	119		T25	80
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	421923	1			T23	31		T25	34		T26	65
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	373663	1			T24	170		T25	203		T26	17
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	498406	1			T23	16		T24	230		T25	111
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2249127	1			T23	130		T24	62		T25	36
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2196539	1			T23	106		T24	225		T25	223
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	504425	1			T23	36		T24	190		T25	62
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	423541	1			T23	22		T25	33		T26	85
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	373320	1			T24	162		T25	283		T26	12
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	497916	1			T23	21		T24	134		T25	115
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2249860	1			T23	122		T24	61		T25	24
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2199283	1			T23	114		T24	239		T25	248
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	505105	1			T23	28		T24	158		T25	91
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	421897	1			T23	26		T25	43		T26	56
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	371112	1			T24	140		T25	267		T26	12
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	497611	1			T23	25		T24	175		T25	79
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2243086	1			T23	129		T24	51		T25	50
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2201963	1			T23	97		T24	219		T25	234
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	500570	1			T23	46		T24	143		T25	81
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	427129	1			T23	12		T25	28		T26	43
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	374726	1			T24	186		T25	268		T26	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	497394	1			T23	31		T24	174		T25	91
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2243519	1			T23	133		T24	61		T25	52
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2205346	1			T23	100		T24	191		T25	302
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	503372	1			T23	30		T24	189		T25	93
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	424006	1			T23	22		T25	14		T26	94
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	373468	1			T24	176		T25	185		T26	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	495157	1			T23	30		T24	156		T25	106
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2241832	1			T23	116		T24	65		T25	44
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2203392	1			T23	108		T24	230		T25	320
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	504446	1			T23	23		T24	126		T25	102
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	423745	1			T23	26		T25	27		T26	68
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	372018	1			T24	198		T25	203		T26	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	499435	1			T23	42		T24	154		T25	56
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2241154	1			T23	130		T24	56		T25	45
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2200751	1			T23	93		T24	224		T25	211
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	506106	1			T23	28		T24	149		T25	82
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	423586	1			T23	20		T25	26		T26	80
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	372926	1			T24	184		T25	231		T26	24
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	500345	1			T23	44		T24	160		T25	157
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2253231	1			T23	128		T24	55		T25	35
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2191192	1			T23	100		T24	213		T25	260
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	501958	1			T23	55		T24	181		T25	74
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	425204	1			T23	14		T25	40		T26	74
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	377006	1			T24	140		T25	282		T26	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	496277	1			T23	18		T24	184		T25	61
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2246910	1			T23	135		T24	68		T25	37
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2198411	1			T23	91		T24	200		T25	272
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	502380	1			T23	26		T24	177		T25	77
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	424797	1			T23	20		T25	23		T26	70
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	376962	1			T24	148		T25	232		T26	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	495408	1			T23	43		T24	180		T25	111
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2246590	1			T23	141		T24	56		T25	35
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2198620	1			T23	83		T24	212		T25	247
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	504607	1			T23	24		T24	161		T25	70
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	421904	1			T23	35		T25	34		T26	53
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	373609	1			T24	140		T25	257		T26	10
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	499538	1			T23	32		T24	204		T25	109
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2240636	1			T23	115		T24	64		T25	44
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2208218	1			T23	104		T24	181		T25	303
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	499308	1			T23	32		T24	152		T25	91
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	425176	1			T23	40		T25	32		T26	43
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	374618	1			T24	196		T25	215		T26	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	496912	1			T23	24		T24	180		T25	67
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2245293	1			T23	129		T24	65		T25	48
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2207562	1			T23	100		T24	230		T25	281
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	501425	1			T23	34		T24	214		T25	137
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	424022	1			T23	18		T25	21		T26	91
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	371223	1			T24	122		T25	146		T26	19
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	495343	1			T23	34		T24	142		T25	119
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2252945	1			T23	136		T24	55		T25	26
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2194361	1			T23	88		T24	197		T25	210
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	504283	1			T23	32		T24	178		T25	79
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	422863	1			T23	26		T25	35		T26	92
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	373816	1			T24	172		T25	260		T26	17
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	496600	1			T23	33		T24	171		T25	142
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2247371	1			T23	133		T24	61		T25	43
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2206469	1			T23	96		T24	213		T25	315
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	505139	1			T23	34		T24	159		T25	99
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	420803	1			T23	34		T25	29		T26	40
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	369752	1			T24	194		T25	214		T26	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	495334	1			T23	18		T24	146		T25	52
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2245280	1			T23	121		T24	55		T25	32
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2201519	1			T23	105		T24	233		T25	196
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	504966	1			T23	25		T24	157		T25	63
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	421590	1			T23	36		T25	39		T26	87
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	372864	1			T24	180		T25	297		T26	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	498649	1			T23	28		T24	148		T25	125
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2248041	1			T23	144		T24	67		T25	41
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2195706	1			T23	94		T24	266		T25	264
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	501744	1			T23	33		T24	128		T25	140
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	425221	1			T23	24		T25	26		T26	58
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	376640	1			T24	164		T25	220		T26	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	497516	1			T23	20		T24	148		T25	61

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal