Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[1]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[2]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[3]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[4]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[5]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[6]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[7]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[8]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[9]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[10]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[11]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[12]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[13]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[14]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[15]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[16]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[17]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[18]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[19]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[20]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[21]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[22]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[23]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[24]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[25]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[26]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[27]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[28]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[29]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[30]	6244868	1			T23	315		T24	773		T25	752
bins_for_gpio_bits[31]	6244868	1			T23	315		T24	773		T25	752

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101546082

1

T23

5984

T24

7148

T25

5344

auto[1]

98289694

1

T23

4096

T24

17588

T25

18720

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101537829

1

T23

5974

T24

7164

T25

5344

auto[1]

98297947

1

T23

4106

T24

17572

T25

18720

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3088349	1			T23	168		T24	184		T25	173
bins_for_gpio_bits[0]	auto[0]	auto[1]	91274	1			T23	7		T24	38		T25	17
bins_for_gpio_bits[0]	auto[1]	auto[0]	91533	1			T23	7		T24	37		T25	17
bins_for_gpio_bits[0]	auto[1]	auto[1]	2973712	1			T23	133		T24	514		T25	545
bins_for_gpio_bits[1]	auto[0]	auto[0]	3076867	1			T23	170		T24	186		T25	199
bins_for_gpio_bits[1]	auto[0]	auto[1]	91287	1			T23	7		T24	39		T25	21
bins_for_gpio_bits[1]	auto[1]	auto[0]	91562	1			T23	7		T24	39		T25	21
bins_for_gpio_bits[1]	auto[1]	auto[1]	2985152	1			T23	131		T24	509		T25	511
bins_for_gpio_bits[2]	auto[0]	auto[0]	3074860	1			T23	166		T24	168		T25	154
bins_for_gpio_bits[2]	auto[0]	auto[1]	91389	1			T23	9		T24	42		T25	19
bins_for_gpio_bits[2]	auto[1]	auto[0]	91678	1			T23	9		T24	42		T25	19
bins_for_gpio_bits[2]	auto[1]	auto[1]	2986941	1			T23	131		T24	521		T25	560
bins_for_gpio_bits[3]	auto[0]	auto[0]	3072686	1			T23	166		T24	176		T25	118
bins_for_gpio_bits[3]	auto[0]	auto[1]	91146	1			T23	9		T24	44		T25	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	91406	1			T23	10		T24	43		T25	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	2989630	1			T23	130		T24	510		T25	614
bins_for_gpio_bits[4]	auto[0]	auto[0]	3077095	1			T23	184		T24	185		T25	164
bins_for_gpio_bits[4]	auto[0]	auto[1]	90891	1			T23	6		T24	37		T25	19
bins_for_gpio_bits[4]	auto[1]	auto[0]	91107	1			T23	7		T24	36		T25	19
bins_for_gpio_bits[4]	auto[1]	auto[1]	2985775	1			T23	118		T24	515		T25	550
bins_for_gpio_bits[5]	auto[0]	auto[0]	3074528	1			T23	177		T24	197		T25	200
bins_for_gpio_bits[5]	auto[0]	auto[1]	91275	1			T23	8		T24	39		T25	27
bins_for_gpio_bits[5]	auto[1]	auto[0]	91520	1			T23	8		T24	39		T25	27
bins_for_gpio_bits[5]	auto[1]	auto[1]	2987545	1			T23	122		T24	498		T25	498
bins_for_gpio_bits[6]	auto[0]	auto[0]	3083625	1			T23	165		T24	210		T25	137
bins_for_gpio_bits[6]	auto[0]	auto[1]	90819	1			T23	7		T24	41		T25	17
bins_for_gpio_bits[6]	auto[1]	auto[0]	91049	1			T23	7		T24	41		T25	17
bins_for_gpio_bits[6]	auto[1]	auto[1]	2979375	1			T23	136		T24	481		T25	581
bins_for_gpio_bits[7]	auto[0]	auto[0]	3088535	1			T23	194		T24	165		T25	116
bins_for_gpio_bits[7]	auto[0]	auto[1]	91508	1			T23	5		T24	40		T25	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	91720	1			T23	5		T24	39		T25	13
bins_for_gpio_bits[7]	auto[1]	auto[1]	2973105	1			T23	111		T24	529		T25	610
bins_for_gpio_bits[8]	auto[0]	auto[0]	3081058	1			T23	182		T24	178		T25	140
bins_for_gpio_bits[8]	auto[0]	auto[1]	90886	1			T23	7		T24	42		T25	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	91146	1			T23	8		T24	41		T25	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	2981778	1			T23	118		T24	512		T25	584
bins_for_gpio_bits[9]	auto[0]	auto[0]	3090348	1			T23	199		T24	188		T25	148
bins_for_gpio_bits[9]	auto[0]	auto[1]	91268	1			T23	3		T24	41		T25	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	91524	1			T23	4		T24	41		T25	21
bins_for_gpio_bits[9]	auto[1]	auto[1]	2971728	1			T23	109		T24	503		T25	562
bins_for_gpio_bits[10]	auto[0]	auto[0]	3078229	1			T23	187		T24	171		T25	143
bins_for_gpio_bits[10]	auto[0]	auto[1]	90857	1			T23	5		T24	32		T25	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	91111	1			T23	5		T24	31		T25	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	2984671	1			T23	118		T24	539		T25	585
bins_for_gpio_bits[11]	auto[0]	auto[0]	3078321	1			T23	202		T24	168		T25	154
bins_for_gpio_bits[11]	auto[0]	auto[1]	91290	1			T23	7		T24	40		T25	17
bins_for_gpio_bits[11]	auto[1]	auto[0]	91556	1			T23	7		T24	40		T25	17
bins_for_gpio_bits[11]	auto[1]	auto[1]	2983701	1			T23	99		T24	525		T25	564
bins_for_gpio_bits[12]	auto[0]	auto[0]	3075384	1			T23	173		T24	185		T25	165
bins_for_gpio_bits[12]	auto[0]	auto[1]	90937	1			T23	9		T24	39		T25	21
bins_for_gpio_bits[12]	auto[1]	auto[0]	91195	1			T23	9		T24	39		T25	21
bins_for_gpio_bits[12]	auto[1]	auto[1]	2987352	1			T23	124		T24	510		T25	545
bins_for_gpio_bits[13]	auto[0]	auto[0]	3095126	1			T23	175		T24	228		T25	175
bins_for_gpio_bits[13]	auto[0]	auto[1]	91090	1			T23	7		T24	38		T25	25
bins_for_gpio_bits[13]	auto[1]	auto[0]	91363	1			T23	7		T24	38		T25	25
bins_for_gpio_bits[13]	auto[1]	auto[1]	2967289	1			T23	126		T24	469		T25	527
bins_for_gpio_bits[14]	auto[0]	auto[0]	3089298	1			T23	172		T24	178		T25	139
bins_for_gpio_bits[14]	auto[0]	auto[1]	90758	1			T23	8		T24	41		T25	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	91029	1			T23	9		T24	40		T25	15
bins_for_gpio_bits[14]	auto[1]	auto[1]	2973783	1			T23	126		T24	514		T25	583
bins_for_gpio_bits[15]	auto[0]	auto[0]	3081982	1			T23	184		T24	197		T25	198
bins_for_gpio_bits[15]	auto[0]	auto[1]	91429	1			T23	9		T24	49		T25	24
bins_for_gpio_bits[15]	auto[1]	auto[0]	91684	1			T23	9		T24	49		T25	24
bins_for_gpio_bits[15]	auto[1]	auto[1]	2979773	1			T23	113		T24	478		T25	506
bins_for_gpio_bits[16]	auto[0]	auto[0]	3086288	1			T23	192		T24	151		T25	135
bins_for_gpio_bits[16]	auto[0]	auto[1]	90844	1			T23	7		T24	35		T25	11
bins_for_gpio_bits[16]	auto[1]	auto[0]	91127	1			T23	7		T24	34		T25	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	2976609	1			T23	109		T24	553		T25	595
bins_for_gpio_bits[17]	auto[0]	auto[0]	3085736	1			T23	182		T24	205		T25	116
bins_for_gpio_bits[17]	auto[0]	auto[1]	91124	1			T23	5		T24	47		T25	15
bins_for_gpio_bits[17]	auto[1]	auto[0]	91357	1			T23	6		T24	47		T25	15
bins_for_gpio_bits[17]	auto[1]	auto[1]	2976651	1			T23	122		T24	474		T25	606
bins_for_gpio_bits[18]	auto[0]	auto[0]	3085036	1			T23	170		T24	180		T25	141
bins_for_gpio_bits[18]	auto[0]	auto[1]	91571	1			T23	5		T24	39		T25	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	91826	1			T23	6		T24	39		T25	17
bins_for_gpio_bits[18]	auto[1]	auto[1]	2976435	1			T23	134		T24	515		T25	577
bins_for_gpio_bits[19]	auto[0]	auto[0]	3079504	1			T23	179		T24	157		T25	141
bins_for_gpio_bits[19]	auto[0]	auto[1]	91035	1			T23	7		T24	38		T25	18
bins_for_gpio_bits[19]	auto[1]	auto[0]	91281	1			T23	8		T24	37		T25	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	2983048	1			T23	121		T24	541		T25	575
bins_for_gpio_bits[20]	auto[0]	auto[0]	3079511	1			T23	179		T24	210		T25	139
bins_for_gpio_bits[20]	auto[0]	auto[1]	91101	1			T23	6		T24	41		T25	20
bins_for_gpio_bits[20]	auto[1]	auto[0]	91386	1			T23	6		T24	40		T25	20
bins_for_gpio_bits[20]	auto[1]	auto[1]	2982870	1			T23	124		T24	482		T25	573
bins_for_gpio_bits[21]	auto[0]	auto[0]	3078514	1			T23	159		T24	159		T25	157
bins_for_gpio_bits[21]	auto[0]	auto[1]	91229	1			T23	6		T24	32		T25	16
bins_for_gpio_bits[21]	auto[1]	auto[0]	91509	1			T23	6		T24	32		T25	16
bins_for_gpio_bits[21]	auto[1]	auto[1]	2983616	1			T23	144		T24	550		T25	563
bins_for_gpio_bits[22]	auto[0]	auto[0]	3078812	1			T23	169		T24	168		T25	135
bins_for_gpio_bits[22]	auto[0]	auto[1]	91748	1			T23	9		T24	38		T25	18
bins_for_gpio_bits[22]	auto[1]	auto[0]	92034	1			T23	9		T24	37		T25	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	2982274	1			T23	128		T24	530		T25	581
bins_for_gpio_bits[23]	auto[0]	auto[0]	3089454	1			T23	191		T24	198		T25	134
bins_for_gpio_bits[23]	auto[0]	auto[1]	90692	1			T23	6		T24	39		T25	15
bins_for_gpio_bits[23]	auto[1]	auto[0]	90939	1			T23	6		T24	38		T25	15
bins_for_gpio_bits[23]	auto[1]	auto[1]	2973783	1			T23	112		T24	498		T25	588
bins_for_gpio_bits[24]	auto[0]	auto[0]	3083037	1			T23	172		T24	206		T25	122
bins_for_gpio_bits[24]	auto[0]	auto[1]	90818	1			T23	8		T24	40		T25	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	91050	1			T23	9		T24	39		T25	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	2979963	1			T23	126		T24	488		T25	600
bins_for_gpio_bits[25]	auto[0]	auto[0]	3081787	1			T23	194		T24	177		T25	124
bins_for_gpio_bits[25]	auto[0]	auto[1]	91041	1			T23	6		T24	41		T25	15
bins_for_gpio_bits[25]	auto[1]	auto[0]	91314	1			T23	6		T24	40		T25	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	2980726	1			T23	109		T24	515		T25	598
bins_for_gpio_bits[26]	auto[0]	auto[0]	3074266	1			T23	181		T24	180		T25	154
bins_for_gpio_bits[26]	auto[0]	auto[1]	90579	1			T23	6		T24	36		T25	13
bins_for_gpio_bits[26]	auto[1]	auto[0]	90854	1			T23	6		T24	36		T25	13
bins_for_gpio_bits[26]	auto[1]	auto[1]	2989169	1			T23	122		T24	521		T25	572
bins_for_gpio_bits[27]	auto[0]	auto[0]	3079379	1			T23	173		T24	234		T25	180
bins_for_gpio_bits[27]	auto[0]	auto[1]	91063	1			T23	8		T24	45		T25	26
bins_for_gpio_bits[27]	auto[1]	auto[0]	91361	1			T23	8		T24	45		T25	26
bins_for_gpio_bits[27]	auto[1]	auto[1]	2983065	1			T23	126		T24	449		T25	520
bins_for_gpio_bits[28]	auto[0]	auto[0]	3088864	1			T23	186		T24	194		T25	125
bins_for_gpio_bits[28]	auto[0]	auto[1]	90969	1			T23	7		T24	39		T25	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	91227	1			T23	8		T24	39		T25	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	2973808	1			T23	114		T24	501		T25	597
bins_for_gpio_bits[29]	auto[0]	auto[0]	3081852	1			T23	194		T24	183		T25	152
bins_for_gpio_bits[29]	auto[0]	auto[1]	91230	1			T23	7		T24	38		T25	19
bins_for_gpio_bits[29]	auto[1]	auto[0]	91461	1			T23	7		T24	37		T25	19
bins_for_gpio_bits[29]	auto[1]	auto[1]	2980325	1			T23	107		T24	515		T25	562
bins_for_gpio_bits[30]	auto[0]	auto[0]	3080319	1			T23	174		T24	173		T25	123
bins_for_gpio_bits[30]	auto[0]	auto[1]	91293	1			T23	8		T24	40		T25	11
bins_for_gpio_bits[30]	auto[1]	auto[0]	91517	1			T23	8		T24	39		T25	11
bins_for_gpio_bits[30]	auto[1]	auto[1]	2981739	1			T23	125		T24	521		T25	607
bins_for_gpio_bits[31]	auto[0]	auto[0]	3083616	1			T23	197		T24	160		T25	188
bins_for_gpio_bits[31]	auto[0]	auto[1]	91122	1			T23	4		T24	35		T25	19
bins_for_gpio_bits[31]	auto[1]	auto[0]	91390	1			T23	4		T24	35		T25	19
bins_for_gpio_bits[31]	auto[1]	auto[1]	2978740	1			T23	110		T24	543		T25	526